Multi-Pass Memory Programming With Pre-Read Voltage Compensation
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Solution Overview
Problem
In multi-pass programming of memory devices, significant threshold voltage shifts due to charge loss during delays between program passes lead to inaccurate programming and bit errors, particularly in non-volatile memory devices like NAND flash, which are exacerbated by temperature and time.
Innovation Solution
Performing a pre-read operation between initial and subsequent program passes to read data from partially written memory cells, allowing for the determination of an updated program voltage that compensates for threshold voltage shifts, thereby reducing bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-pass programming is used to program memory devices, then programming capacity and flexibility are improved, but threshold voltage shifts due to charge loss during delays between passes cause programming inaccuracy and bit errors
Solution Approach 1:
The patent performs a pre-read operation between the initial and subsequent program passes to detect threshold voltage shifts before the subsequent programming occurs. This preliminary detection allows the system to identify charge loss and adjust programming parameters accordingly, preventing programming inaccuracies before they affect final data integrity.
Solution Approach 2:
The patent implements a feedback mechanism where the pre-read operation results are used to determine whether to adjust the program voltage for the subsequent program pass. The system continuously monitors threshold voltage shifts and adjusts programming parameters based on this feedback, ensuring accurate programming despite charge loss during delays between passes.
2Productivity
If delay time between program passes is extended, then programming flexibility is improved, but charge loss increases leading to greater threshold voltage shifts and more bit errors
Solution Approach 1:
The pre-read operation is performed before the subsequent program pass to detect any threshold voltage shifts that may have occurred during the delay period. This allows the system to identify charge loss early and adjust programming parameters before executing the final programming operation, maintaining data accuracy regardless of delay duration.
Solution Approach 2:
The patent dynamically adjusts the program voltage parameter based on detected threshold voltage shifts. When charge loss is detected through the pre-read operation, the system modifies the program voltage for the subsequent pass to compensate for the shifts, thereby maintaining programming accuracy even when delay times vary.
3Speed
If temperature increases, then device operation speed is improved, but charge loss accelerates causing larger threshold voltage shifts and increased bit errors
Solution Approach 1:
The pre-read operation provides feedback about threshold voltage shifts that have occurred, allowing the system to detect temperature-related charge loss. Based on this feedback, the system adjusts the program voltage for the subsequent pass to compensate for thermal effects, maintaining programming accuracy despite increased operation temperatures.
Solution Approach 2:
The patent adjusts the program voltage parameter in response to detected threshold voltage shifts caused by temperature increases. By modifying this critical parameter based on real-time detection, the system compensates for accelerated charge loss at higher temperatures and maintains programming precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Compensating for threshold voltage shifts during multi-pass programming reduces bit errors and enhances the reliability and accuracy of memory sub-systems by ensuring accurate programming.
Implementation Method 1
significant threshold voltage shifts due to charge loss during delays between program passes
Data Source
AI summary
An apparatus includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first program pass of a multi-pass program operation to partially program one or more memory cells of the memory array to a first program level that is different than a final program level. The operations include causing a pre-read operation to read data corresponding to the first program pass. The operations further include determining an updated second program voltage of a second program pass of the multi-pass program operation based on the pre-read operation.


