Capacitorless DRAM Gate Structure for Capacitive Coupling Noise
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Solution Overview
Problem
Capacitorless single-transistor DRAMs experience large capacitive coupling between the word line and the floating body, leading to noise transmission during data read or write operations, causing misreading or erroneous rewriting of stored data.
Innovation Solution
A memory device structure with a semiconductor base material arranged vertically, featuring separate gate conductor layers with controlled voltages applied to impurity layers and gate conductor layers to manage capacitive coupling, using a sense amplifier circuit for concurrent data reading and refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitorless single-transistor DRAM structure is used, then packaging density is improved, but noise interference from capacitive coupling increases
Solution Approach 1:
The gate structure is segmented into two separate gate conductor layers (first gate conductor layer and second gate conductor layer) with different capacitances. The first gate conductor layer has higher gate capacitance to suppress noise, while the second has lower capacitance. This segmentation allows independent optimization of noise suppression and functionality, resolving the contradiction between compact structure and noise interference.
Solution Approach 2:
Different regions of the gate structure are given different electrical properties. The first gate conductor layer is designed with higher capacitance characteristics specifically for noise suppression, while the second layer maintains lower capacitance for proper transistor operation. This local differentiation of electrical properties allows the system to achieve both high density and low noise.
2Speed
If word line voltage swings during read/write operations, then data operation speed is improved, but capacitive coupling noise to floating body increases
Solution Approach 1:
The first gate conductor layer acts as an intermediary between the word line and the floating body. It provides a capacitive coupling path with higher capacitance that dominates the total coupling, thereby shielding the floating body from noise caused by word line voltage swings. This intermediary structure enables fast data operations while suppressing noise transmission.
Solution Approach 2:
The high-capacitance first gate conductor layer is positioned to provide beforehand cushioning against capacitive coupling noise. By establishing a dominant capacitive path before noise can affect the floating body, it cushions the system against the harmful effects of word line voltage swings during read/write operations.
3Device complexity
If single gate structure is used, then device complexity is reduced, but noise suppression capability is insufficient
Solution Approach 1:
The gate structure is divided into two conductor layers with different capacitance values. This segmentation provides noise suppression capability that a single gate cannot achieve, while maintaining relatively simple overall structure. The first layer suppresses noise and the second layer maintains functionality, resolving the contradiction between simplicity and noise suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces noise interference by controlling capacitive coupling, ensuring stable data retention and accurate data reading/writing, making capacitorless DRAMs viable for practical use.
Implementation Method 1
a refresh operation of forming positive hole groups by an impact ionization phenomenon in the channel semiconductor layer
Data Source
AI summary
A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.