NAND Memory Array Layout With Parallel String Connection
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Solution Overview
Problem
Existing NAND flash memory arrays face challenges in optimizing the parallel connection of series-connected memory cells, leading to inefficiencies in current flow and operational limitations.
Innovation Solution
The implementation of multiple decks of series-connected memory cells with selectively connected segments, allowing for parallel current paths through the array structure, and the use of pre-configured select gates with programmable and non-programmable threshold voltages to enhance conductivity and control current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If series-connected memory cells are arranged in traditional NAND flash memory arrays, then memory density is achieved, but current flow efficiency and operational performance are limited
Solution Approach 1:
The memory array is divided into multiple decks, with each deck containing a portion of the series-connected memory cells. This segmentation allows different decks to be selectively connected in parallel, improving current flow efficiency while maintaining the series connection benefits for memory density. The segmentation enables flexible configuration where only necessary decks are activated for each operation.
Solution Approach 2:
The patent introduces a vertical dimension to the traditional planar NAND flash structure by stacking multiple decks vertically. This dimensional change allows parallel connection of series strings across different vertical levels, significantly improving current flow efficiency without increasing the footprint area, thereby resolving the contradiction between productivity and device complexity.
2Productivity
If multiple decks of series-connected memory cells are connected in parallel, then current flow efficiency improves, but control and selection complexity increases
Solution Approach 1:
The select gates are configured with programmable threshold voltages that can be dynamically adjusted based on operational requirements. This dynamic control allows the system to selectively activate or deactivate specific decks and strings, optimizing operational performance while managing control complexity through adaptive voltage adjustment rather than fixed complex routing.
Solution Approach 2:
The patent utilizes threshold voltage as a controllable parameter to manage the parallel connection of multiple decks. By programming select gates with different threshold voltages, the system can selectively enable or disable specific memory strings based on operational needs, thereby improving operational performance while maintaining manageable control complexity through parameter-based selection.
3Ease of operation
If pre-configured select gates with programmable threshold voltages are used, then conductivity control improves, but manufacturing and programming complexity increases
Solution Approach 1:
The select gates are pre-configured during manufacturing with programmable threshold voltage capabilities, and the actual programming of specific threshold values is performed as a preliminary step before operational use. This preliminary action separates the manufacturing process from the operational configuration, allowing standard manufacturing processes to produce programmable gates while the specific threshold programming is done once during device initialization or fabrication, thereby improving ease of operation without significantly complicating manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the efficiency of current flow and operational performance in NAND flash memory arrays by enabling parallel connections and optimizing the conductive pathways, enhancing overall array performance.
Implementation Method 1
the use of pre-configured select gates with programmable and non-programmable threshold voltages to enhance conductivity and control current flow
Data Source
AI summary
Arrays of memory cells including a plurality of strings of series-connected memory cells, a data line, a common source, and a conductive element between the data line and the common source, wherein the conductive element has a first side facing the common source and a second side facing the data line. Each of the strings of series-connected memory cells including a respective first subset of memory cells of a respective plurality of memory cells between the first side of the conductive element and the common source, and selectively connected to the conductive element on the first side of the conductive element. Each of the strings of series-connected memory cells including a respective second subset of memory cells of its respective plurality of memory cells between the second side of the conductive element and the data line.