3D Flash Memory Back Gate Structure With Ferroelectric Storage

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Solution Overview

Problem

Three-dimensional flash memory arrays experience degradation in cell characteristics and reliability due to increased integration, particularly in vertical memory cells.

Innovation Solution

Incorporation of a ferroelectric layer between word lines and a channel layer with a back gate structure inside the channel layer, utilizing the ferroelectric layer for data storage and applying specific voltages to the back gate for programming, erasing, and reading operations to improve cell characteristics and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If cells are vertically stacked to increase integration, then the degree of integration is improved, but cell characteristics and reliability deteriorate

Engineering Contradiction:

Improveintegration densityVSAvoidcell reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from vertical stacking to horizontal scaling by introducing a back gate structure that enables increased integration through lateral expansion rather than vertical growth. This dimensional shift allows cells to be arranged horizontally with improved characteristics while maintaining high integration density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention modifies key structural parameters by introducing a back gate configuration and adjusting cell geometry to optimize horizontal scaling. These parameter changes enable improved cell characteristics and reliability while achieving the desired integration density through lateral rather than vertical expansion.

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If vertical memory cells are used to increase integration, then the degree of integration is improved, but cell characteristics and reliability degrade

Engineering Contradiction:

Improveintegration densityVSAvoidcell characteristics

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent replaces vertical memory cell architecture with a horizontal scaling approach using back gate structures. This dimensional transformation allows integration density to increase through lateral cell arrangement while preserving cell characteristics and reliability that degrade in vertical configurations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention employs composite structural elements including the back gate configuration combined with modified cell geometry. This composite approach enables simultaneous achievement of high integration density through horizontal scaling while maintaining the electrical and structural characteristics necessary for reliable memory operation.

Inventive Principle:

Principle #40Composite materials

3Ease of manufacture

If conventional flash memory structure is used, then manufacturing simplicity is maintained, but cell characteristics and reliability are poor

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidmemory reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent modifies conventional flash memory parameters by introducing the back gate structure and adjusting cell geometry. These parameter changes improve cell characteristics and reliability while maintaining manufacturing processes that are sufficiently simplified for practical production, achieving a balance between reliability improvement and manufacturing feasibility.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances cell characteristics and reliability while allowing for improved horizontal scaling by using the ferroelectric layer as data storage, enabling faster and more reliable memory operations.

Implementation Method 1

a ferroelectric layer extending in the one direction to surround the channel layer... the ferroelectric layer is used as data storage by changing and maintaining states of charges

Methodology Applied

Scientific EffectFerroelectric effect:

Implementation Method 2

applying specific voltages to the back gate for programming, erasing, and reading operations

Methodology Applied

Scientific EffectElectric field control: Electric Field

Data Source

PatentUS20260089970A1Three-dimensional flash memory using ferroelectric layer on basis of back gate structure

Publication Date: 2026.03.26 SAMSUNG ELECTRONICS CO LTD

AI summary

Disclosed is a three-dimensional flash memory using a ferroelectric layer on the basis of a back gate structure. According to an embodiment, a three-dimensional flash memory comprises: a plurality of word liens extending on a substrate in a horizontal direction and sequentially stacked; and a plurality of strings extending through the plurality of word lines on the substrate in one direction, each of the plurality of strings including a channel layer extending in the one direction and a ferroelectric layer extending in the one direction to surround the channel layer, wherein a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate are disposed inside the channel layer, and the channel layer and the ferroelectric layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the ferroelectric layer is formed of a ferroelectric material and used as data storage by changing and maintaining the states of electric charges.