3D Memory Programming Using Fail Bit Read Feedback
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Solution Overview
Problem
The existing 3D memory technologies face challenges in efficiently programming memory cells with high storage density due to the need for multiple write operations and the subsequent requirement for error correction processing, which complicates the program efficiency and increases error rates.
Innovation Solution
A method involving a first program operation followed by a read operation using preset read voltages to determine the fail bit count, allowing a second program operation without error correction when the fail bit count meets certain requirements, thereby optimizing program efficiency and reducing error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple program operations are performed on memory cells to achieve high storage density, then the storage capacity is improved, but the program efficiency deteriorates due to repeated write operations
Solution Approach 1:
The patent performs a read operation after the first program operation to determine the fail bit count before proceeding to the second program operation. This preliminary check allows the system to identify memory cells that require additional programming, thereby optimizing the multi-step programming process for high storage density while maintaining efficiency.
2Reliability
If error correction processing is performed during program operations, then the data accuracy is improved, but the program efficiency deteriorates due to complex processing steps
Solution Approach 1:
The patent performs a read operation to determine the fail bit count before the second program operation, allowing preliminary identification of cells needing correction. This enables targeted error correction only where necessary, rather than applying complex error correction processing to all cells, thus maintaining data accuracy while improving program efficiency.
Solution Approach 2:
The memory system uses the read operation results to self-determine which memory cells require error correction or additional programming. By autonomously identifying fail bits and adjusting the programming strategy accordingly, the system reduces the need for complex external error correction processing, thereby maintaining accuracy while enhancing efficiency.
3Quantity of substance
If multiple program operations are performed on memory cells, then the storage density is improved, but the error rate worsens due to repeated write operations
Solution Approach 1:
The patent implements a feedback mechanism where the result of the read operation (fail bit count) is used to determine whether to perform the second program operation. This feedback loop allows the system to monitor and control the error rate introduced by multiple program operations, ensuring high storage density while maintaining reliability by applying additional programming only when necessary.
Data Source
AI summary
The present disclosure discloses a memory, a memory system, a program method of a memory, and an electronic apparatus, relating to the technical field of memories. The memory includes a memory array and a peripheral circuit, wherein the memory array includes memory cells; the peripheral circuit is configured to perform a first program operation on the memory cells, perform a read operation on a memory page through a preset read voltage, and perform a second program operation on the memory cells in a case where a fail bit count read based on the read voltage meets a preset requirement.