3D Memory Gate Stack Layout for Lower Channel Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of scaling down memory devices is exacerbated by the difficulty in etching holes with large aspect ratios and using polycrystalline silicon as a channel material, which increases resistance and limits the number of stackable layers, affecting performance and capacity.
Innovation Solution
A memory device with vertically stacked device layers and a gate stack that extends through these layers, featuring a bended shape and separate processing channels or holes, allowing for the use of single crystal materials and reducing etching difficulties, while incorporating conductive metal layers for reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers is increased to increase memory capacity, then memory capacity is improved, but device performance deteriorates due to greater resistance from polycrystalline silicon channel material
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to single crystal silicon for the channel region. This material parameter change reduces resistance and maintains device performance even as the number of stacked layers increases, thereby resolving the contradiction between increasing memory capacity and maintaining device performance
Solution Approach 2:
The patent uses a composite structure where single crystal silicon forms the channel region while polycrystalline silicon may be used for other regions. This composite approach allows optimization of electrical properties in the channel region while maintaining the benefits of stacked architecture for capacity expansion
2Quantity of substance
If the number of stacked layers is increased to increase memory capacity, then memory capacity is improved, but the difficulty of etching holes increases due to large aspect ratios
Solution Approach 1:
The patent divides the stacked structure into multiple device layers (first device layers and second device layers) with separate processing channels. This segmentation allows each etching operation to work on manageable sections rather than attempting to etch through the entire stack in one operation, reducing the effective aspect ratio and etching difficulty while still achieving high memory capacity through stacking
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure with vertical channels. By utilizing the vertical dimension and creating separate processing channels at different heights, the patent achieves high capacity without requiring single ultra-deep etching operations, thus managing aspect ratio challenges
3Ease of manufacture
If polycrystalline silicon is used as channel material to simplify manufacturing, then ease of manufacture is improved, but resistance increases affecting device performance
Solution Approach 1:
The patent applies local quality by using single crystal silicon specifically for the channel region where low resistance is critical, while other regions of the device may continue to use polycrystalline silicon. This localized material optimization ensures high performance in the channel while maintaining overall manufacturing feasibility
Solution Approach 2:
The patent changes the crystalline structure parameter of the channel material from polycrystalline to single crystal. This parameter change reduces resistance and improves carrier mobility in the channel region, directly enhancing device performance while the rest of the device structure can maintain manufacturing simplicity
Data Source
AI summary
Disclosed are a memory device, a method of manufacturing the memory device, and an electronic device. The memory device may include: a plurality of first device layers, each including first and second source/drain regions and a channel region; a plurality of second device layers stacked on the first device layers, each including third and fourth source/drain regions and a channel region; and a gate stack extending vertically to pass through the first and second device layers. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and each device layer, and a memory cell is defined at an intersection of the gate stack and each device layer. The gate stack has a surface in a bended shape at a position where the plurality of first device layers are adjacent to the plurality of second device layers.