Dummy Bit Line Layout for Noise-Isolated Nonvolatile Memory Reads

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Solution Overview

Problem

Flash memory devices experience reduced reliability due to noise interference from the common source line affecting bit lines during read operations, which affects the accuracy and integrity of data storage.

Innovation Solution

Incorporation of dummy bit lines controlled by a dummy bit line driver to isolate noise from the common source line, maintaining bit line voltages and enhancing operational reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a common source line is used to connect memory cells, then device complexity is reduced and ease of manufacture is improved, but noise is introduced to bit lines causing reduced reliability

Engineering Contradiction:
Improvedata sensing accuracyVSAvoidbit line layout complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bit line system is segmented into real bit lines for data sensing and dummy bit lines for noise isolation. The dummy bit lines are positioned adjacent to the common source line to intercept noise before it reaches the real bit lines, effectively segmenting the noise path from the data path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dummy bit lines serve as intermediary elements between the common source line and the real bit lines. These dummy bit lines absorb and shield against noise from the common source line, acting as a protective mediator that prevents noise from reaching the sensitive real bit lines used for data sensing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dummy bit lines are added to isolate noise, then reliability is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveoperational reliabilityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The dummy bit lines are merged with the existing bit line structure and fabrication process. They are formed using the same material layers and patterning steps as the real bit lines, allowing both types of bit lines to be manufactured simultaneously without requiring separate fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Instead of redesigning the entire bit line system, only partial dummy bit lines are added in specific locations where noise from the common source line most strongly affects real bit lines. This partial action approach provides sufficient noise isolation without the excessive complexity of a complete system redesign.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If dummy bit lines are used to maintain bit line voltages, then noise interference is minimized, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy bit lines are designed to automatically maintain proper voltage levels through their inherent electrical characteristics and connection to voltage reference nodes. They self-regulate to provide noise isolation without requiring complex active control circuits or additional control logic, thus maintaining data integrity while minimizing added complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4060669B1Nonvolatile memory device
Publication Date: 2026.03.25 SAMSUNG ELECTRONICS CO LTD
  • EP4060669B1 patent drawingFigure 1
  • EP4060669B1 patent drawingFigure 2
  • EP4060669B1 patent drawingFigure 3

AI summary

A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.