Select Gate Threshold Scan Timing for NAND Memory Reliability
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Solution Overview
Problem
Existing memory devices face reliability issues due to threshold voltage degradation of select gate devices, which can lead to improper functioning and data integrity problems, and current threshold voltage integrity scans are inefficient with constant program/erase cycle intervals, causing host device timeouts and quality of service impacts.
Innovation Solution
Adaptive scan frequency is implemented in memory sub-systems to determine the number of program/erase cycles and adjust the frequency of threshold voltage integrity scans based on the rate of change in select gate device threshold voltages, performing touch-up operations when necessary to maintain optimal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If constant program/erase cycle intervals are used for threshold voltage integrity scans, then scan simplicity is maintained, but quality of service deteriorates due to host device timeouts and excessive scan frequency
Solution Approach 1:
The patent implements dynamic scan frequency adjustment based on the actual degradation rate of select gate devices. The controller monitors threshold voltage changes over program/erase cycles and adapts the scan interval accordingly - increasing frequency when degradation is rapid and decreasing when stable, thus optimizing quality of service while maintaining operational simplicity through automated adaptation
Solution Approach 2:
The patent changes the time parameter (scan interval) from a fixed constant to a variable that adapts based on monitored conditions. By adjusting the scan frequency dynamically according to observed threshold voltage degradation rates, the system resolves the contradiction between simple constant intervals and service-optimized variable intervals
2Reliability
If frequent threshold voltage integrity scans are performed, then reliability monitoring is improved, but productivity deteriorates due to host device timeouts and quality of service impacts
Solution Approach 1:
The system dynamically adjusts scan frequency based on actual device degradation behavior. When threshold voltage changes rapidly, scans are performed more frequently to ensure reliability. When degradation is slow or stable, scan frequency is reduced to minimize quality of service impacts, thus resolving the contradiction between thorough monitoring and system performance
Solution Approach 2:
The controller uses feedback from previous scan results to determine future scan timing. By analyzing the rate of threshold voltage change observed in prior scans, the system intelligently schedules subsequent scans - increasing frequency when reliability concerns arise and decreasing when the device is stable, thereby balancing reliability monitoring with productivity
3Reliability
If selective gate devices are monitored continuously, then threshold voltage shifts are prevented, but loss of time occurs due to excessive scan operations
Solution Approach 1:
The patent implements periodic scans with variable intervals rather than continuous monitoring. The scan period is dynamically adjusted based on observed degradation rates - shorter periods when threshold voltage is changing rapidly and longer periods when stable - thus preventing excessive threshold voltage shifts while minimizing time loss from unnecessary scans
Solution Approach 2:
The system transitions from fixed periodic scanning to dynamic periodic scanning where the interval adapts to actual device conditions. This resolves the contradiction by performing scans frequently enough to prevent threshold voltage shifts when needed, but infrequently enough to minimize time loss when the device is stable
Data Source
AI summary
A processing device, operatively coupled with a memory device, determines a number of program/erase cycles performed on a block of the memory device. The processing device determines that the number of program/erase cycles performed on the block satisfies a first threshold criterion, wherein the first threshold criterion corresponds to a frequency interval for performing a threshold voltage integrity scan on the block. The processing device performs a threshold voltage integrity scan on the block to determine an error count associated with a current threshold voltage of at least one select gate device of the block. Responsive to the error count associated with the current threshold voltage of the at least one select gate device satisfying a second threshold criterion, the processing device determines a rate of change associated with the current threshold voltage of the at least one select gate device. The processing device updates, based on the rate of change, the frequency interval for performing a threshold voltage integrity scan on the block.