Quad-bit Flash Memory Cell Using Single Program Erase Entity
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Solution Overview
Problem
Conventional flash memory devices lack the ability to perform single logical cell erasure and support byte alterability, as they can only erase data in large sectors or blocks, limiting their programming and storage capabilities.
Innovation Solution
The implementation of a single program and erase entity as a single logical cell, comprising neighboring drain/source regions of two adjacent physical memory cells, allows for independent programming and erasure of each cell, enabling quad or more bit storage and facilitating single logical cell erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional flash memory devices use sector or block based erasure, then erasure operations can be performed on large units of memory, but single logical cell erasure and byte alterability are not supported
Solution Approach 1:
The patent divides a physical memory cell into multiple independently controllable regions by introducing separate control gates (first control gate and second control gate) that can selectively program or erase specific portions of the memory cell. This segmentation allows single logical cell erasure while maintaining the physical cell structure, resolving the contradiction between operational flexibility and device complexity.
Solution Approach 2:
The patent implements dynamic control of memory cell states through independent control gates that can selectively apply program or erase voltages to different regions of the same physical cell. This dynamic controllability enables byte alterability and single logical cell erasure without requiring additional physical cells, thus improving ease of operation without proportionally increasing device complexity.
2Quantity of substance
If each physical memory cell stores only one bit, then the memory structure is simple, but storage density is limited
Solution Approach 1:
The patent combines multiple data states within a single physical memory cell by utilizing different charge trapping levels in the charge trapping layer. Each physical cell can store multiple bits by representing different charge quantities as distinct data states (e.g., 4-bit storage with 16 different charge levels), thereby increasing storage capacity without increasing the number of physical cells or significantly complicating the device structure.
Solution Approach 2:
The patent changes the parameter of charge quantity in the charge trapping layer to encode multiple bits of information. By controlling the amount of charge trapped (rather than just presence/absence), the memory cell can represent multiple discrete states (e.g., 0-15 units of charge for 4-bit storage). This parameter-based encoding increases storage density while maintaining the fundamental memory cell structure.
3Quantity of substance
If flash memory devices use multi-level cell storage, then storage density increases, but programming and erasure flexibility decreases
Solution Approach 1:
The patent segments the control of charge trapping into multiple independent control gates, each capable of selectively programming or erasing specific regions of the memory cell. This segmentation allows flexible manipulation of multi-level data states, enabling operations such as single logical cell erasure and byte alterability even when multiple bits are stored in each physical cell, thus maintaining adaptability while increasing storage density.
Data Source
AI summary
Flash memory systems and methodologies are provided herein for facilitating single logical cell erasure and quad or more bit storage in a flash device. The single logical cell erasure can be accomplished by employing a single program and erase entity as a single logical cell. The single program and erase entity is a combination of neighboring drain/source regions of two adjacent physical memory cells. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis. The memory cells can contain four or more data states, and each of the two adjacent memory cells in the single program and erase entity can be programmed independently from each other. As a result, the single program and erase entity can store four or more bits.