Nonvolatile Memory Erase Verification Segmentation

The patent divides the verification process into segments by identifying and separately handling failed word lines. Instead of uniformly verifying all word lines, the system segments verification into: (1) initial comprehensive verification, (2) targeted re-verification of only failed word lines, and (3) final confirmation. This segmentation allows the system to maintain reliability by verifying all word lines initially while reducing total operation time by focusing subsequent verification efforts only on failed segments.

The patent applies preliminary action by performing an initial comprehensive verification of all word lines before determining the verification strategy. This preliminary verification identifies which word lines have failed, enabling the system to plan targeted re-verification of only those specific word lines. The preliminary action of identifying failures upfront prevents unnecessary re-verification of already-passed word lines, thus reducing total operation time while maintaining reliability.

The patent segments the verification workload by identifying failed word lines and separating them from successfully verified word lines. The verification process is divided into: (1) initial batch verification of all word lines, (2) targeted re-verification of only failed word lines, and (3) final verification. This segmentation improves productivity by eliminating redundant verification of already-passed word lines while maintaining reliability through comprehensive initial verification and focused re-verification of failures.

The patent applies partial action by performing verification only on the necessary subset of word lines at each stage. Instead of repeatedly verifying all word lines (excessive action), the system performs partial verification focused only on failed word lines after the initial comprehensive check. This partial action approach maintains reliability by ensuring all word lines are initially verified while improving productivity by avoiding redundant verification cycles on already-passed word lines.

The patent applies local quality by implementing differential verification and voltage adjustment strategies for different word line groups. Specifically, passed word lines receive standard verification and no further adjustment, while failed word lines receive targeted re-verification with adjusted erase voltages. This local quality approach improves manufacturing precision by optimizing verification parameters for each word line's specific status while avoiding unnecessary complexity in the control logic for word lines that already pass verification.

The patent changes verification parameters (specifically erase voltage levels) based on the verification status of each word line. When word lines fail initial verification, the system adjusts the erase voltage parameter and performs targeted re-verification. This parameter change approach improves manufacturing precision by adapting verification conditions to the specific needs of failed word lines. The complexity increase is managed by implementing these parameter changes only for failed word lines rather than all word lines, using conditional logic that adds complexity only where necessary.