2T Vertical Memory Cell Shield Structures for Capacitive Coupling
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints, leading to excessive capacitive coupling between adjacent memory cells, which affects operational efficiency.
Innovation Solution
The implementation of a memory device with a 2T (two-transistor) cell structure, including a charge storage structure and shield structures to reduce capacitive coupling, allowing for a smaller footprint and improved read signal margin, utilizing a single access line to control both transistors and incorporating cross-point gain cell structures for efficient data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then device storage density is improved, but capacitive coupling between adjacent memory cells increases
Solution Approach 1:
A shield structure is introduced as an intermediary element positioned between adjacent charge storage structures. The shield structure includes a first conductive portion coupled to a first potential and a second conductive portion coupled to a second potential, creating an electric field that counteracts capacitive coupling between adjacent memory cells. This intermediary structure effectively blocks the harmful capacitive coupling while allowing the memory cell size to remain small for high storage density.
Solution Approach 2:
The shield structure is configured to preemptively counteract capacitive coupling before it can affect memory cell operation. By positioning the shield between charge storage structures and applying appropriate potentials to its conductive portions, the system creates a protective electric field that prevents harmful capacitive interactions from developing, thereby maintaining signal integrity in high-density configurations.
2Ease of manufacture
If conventional memory cell structures are used, then fabrication is simpler, but physical limitations prevent further size reduction
Solution Approach 1:
The memory cell structure transitions from a planar two-dimensional layout to a three-dimensional vertical architecture. The charge storage structure extends in the vertical direction with a bottom electrode, dielectric layer, and top electrode configuration, allowing the memory cell to achieve smaller footprint area while maintaining sufficient storage capacity. This dimensional change enables continued scaling despite conventional fabrication limitations.
Solution Approach 2:
The charge storage structure employs a nested configuration where the dielectric layer is positioned between the bottom electrode and top electrode, creating a compact vertical stack. This nested arrangement allows multiple functional layers to be integrated within a small vertical space, reducing the overall memory cell footprint while maintaining the necessary electrical isolation and storage functionality.
3Productivity
If access lines are increased to control more transistors, then data access capability is improved, but power dissipation increases
Solution Approach 1:
The shield structure serves multiple functions simultaneously: it reduces capacitive coupling between adjacent memory cells, provides electrical isolation for signal integrity, and can be configured to assist in bit line precharging during read operations. By making the shield structure multi-functional, the patent reduces the need for additional dedicated access lines and structures, thereby lowering overall power dissipation while maintaining data access capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reduced power dissipation, improved processing efficiency, and enhanced operational performance by minimizing capacitive coupling and allowing for cross-point operations with a single access line, thereby improving storage density without compromising signal integrity.
Implementation Method 1
excessive capacitive coupling between elements of adjacent memory cells
Implementation Method 2
The memory device can include shield structures between charge storage structures of adjacent memory cells
Data Source
AI summary
Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.