Write Assistance Cell Mitigates Parasitic Effects in IC Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face challenges in maintaining high operation reliability due to increased parasitic elements from reduced wiring widths, intervals, and heights, which affect performance, especially in cell arrays with memory cells.
Innovation Solution
The integration of write assistance cells with the same transistor configuration and footprint as memory cells, along with a row driver that activates these cells during write operations, helps mitigate the impact of parasitic elements by compensating for bit line effects and improving writing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring widths, intervals, and heights are reduced for high integration, then integration density is improved, but parasitic elements increase and reliability deteriorates
Solution Approach 1:
The write assistance cell performs preliminary actions by pre-charging bit lines and pre-conditioning the write path before the actual write operation. This preliminary action compensates for the increased parasitic effects in scaled-down wiring, ensuring that the main write operation can proceed reliably despite the reduced wiring dimensions and increased integration density.
2Use of energy by moving object
If power supply voltage is reduced for lower power consumption, then power efficiency is improved, but the impact of parasitic elements increases and writing reliability deteriorates
Solution Approach 1:
The write assistance cell applies preliminary anti-action by pre-charging the bit lines to the appropriate voltage levels and pre-establishing the write current path. This counteracts the weakened drive capability caused by reduced power supply voltage and compensates for the increased parasitic voltage drops, ensuring reliable writing despite lower operating voltages.
3Reliability
If write assistance cells are added to mitigate parasitic effects, then writing reliability is improved, but device complexity increases
Solution Approach 1:
The write assistance cell uses the same transistor configuration and layout as the memory cells, allowing it to serve dual purposes: maintaining regular cell array structure while providing write assistance functionality. This universal design minimizes the increase in device complexity by reusing existing cell structures rather than introducing entirely new components.
Data Source
AI summary
An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.