Memory Redundancy Architecture Using Binary Repair Cells
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Solution Overview
Problem
Conventional memory circuits with row and column redundancy require significant die space and I/O resources due to the need for decoding redundancy information and complex bus routing, which complicates design and increases resource demands.
Innovation Solution
The proposed solution involves storing redundancy identification information in binary storage cells, such as repair memory cells, which use a set signal to indicate whether a row or column unit is faulty, allowing the X decoder or Y driver to substitute a redundant unit without additional decoding logic or I/O resources, thereby simplifying the architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row and column redundancy schemes are implemented with decoding logic and redundancy information buses, then memory reliability is improved through fault detection and substitution, but die area and device complexity increase due to additional decoding portions and bus routing
Solution Approach 1:
The patent extracts the redundancy identification information from the complex decoding process and stores it separately in repair memory cells. This separation removes the burden of decoding redundancy information from the X decoder and Y driver, thereby reducing their complexity while maintaining the reliability benefits of redundancy
Solution Approach 2:
The patent creates a simplified copy of the row-unit and column-unit identification information and stores it in repair memory cells. This copying approach allows the system to reference pre-stored redundancy information instead of performing complex decoding operations in real-time
2Reliability
If redundancy information is stored and decoded using conventional methods, then faulty memory units can be identified and substituted, but I/O resource requirements increase due to additional pins for redundancy information
Solution Approach 1:
The repair memory cells serve multiple functions: they store both the redundancy identification information and can be used as part of the functional memory array. This multi-functionality eliminates the need for dedicated I/O resources solely for redundancy management
Solution Approach 2:
The patent merges the redundancy information storage function with the existing memory array structure by using repair memory cells that are integrated into the array. This integration combines the redundancy management function with the data storage function, reducing separate I/O requirements
3Area of stationary object
If repair memory cells are integrated into the memory array, then die area is reduced by eliminating separate decoding logic, but the memory array structure becomes more complex
Solution Approach 1:
The patent segments the memory array into functional units (row-units and column-units) with associated repair memory cells. This segmentation allows for modular organization where each segment manages its own redundancy independently, making the overall complexity manageable despite the integrated structure
Data Source
AI summary
In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.