Anti-Fuse Memory Cell Layout for Disturbance-Free High Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile semiconductor storage devices face challenges in preventing unintended charge injection and disturbance in memory cells, while also requiring downsizing to increase memory cell density.
Innovation Solution
The memory cell design includes a fin structure with a memory gate and select gate structures that form a depleted layer to prevent charge injection, using a quantum tunneling effect for programming, and reducing the distance between drain and source regions to minimize potential differences and electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high charge storage gate voltage is applied to the memory gate line to inject charge into the charge storage layer, then programming is achieved, but unintended charge injection and disturbance occur in memory cells that should not be programmed
Solution Approach 1:
The patent divides the gate structure into multiple segments: a first select gate structure, a memory gate structure, and a second select gate structure. This segmentation allows independent control of charge injection - the first select gate controls charge injection from the bit line, while the second select gate controls charge injection from the source line, enabling precise programming without disturbance to adjacent cells
Solution Approach 2:
The patent introduces a channel layer as an intermediary between the bit line and the charge storage layer. This channel layer acts as a controlled pathway that only allows charge injection when both select gates are properly activated, preventing direct charge injection into the charge storage layer when it should remain unchanged
2Reliability
If high bit voltage is applied to the channel layer to prevent charge injection, then disturbance is reduced, but the voltage difference between memory gate electrode and channel layer decreases
Solution Approach 1:
The patent dynamically adjusts the voltage applied to the channel layer based on the programming state. During programming, the channel layer voltage is controlled to enable quantum tunneling; during non-programming operations, the channel layer voltage is adjusted to prevent charge injection while maintaining sufficient voltage difference for proper memory gate control
3Productivity
If memory cell size is reduced to increase density, then more memory cells can be arranged, but prevention of disturbance becomes more difficult
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional vertically stacked gate structures. By stacking the first select gate, memory gate, and second select gate vertically, the patent achieves higher integration density while maintaining sufficient lateral spacing between adjacent memory cells to prevent disturbance, effectively utilizing the vertical dimension to resolve the density-reliability tradeoff
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents charge injection and disturbance, enabling downsizing of memory cells for higher density while maintaining fast operation and reducing voltage requirements.
Implementation Method 1
charge is injected into the charge storage layer due to a quantum tunneling effect caused by a large voltage difference between the bit voltage and the memory gate voltage
Data Source
AI summary
In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.