3D NOR Flash Memory Pillar Structure for High Integration
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Solution Overview
Problem
NOR flash memory faces challenges with high integration and operating current requirements, leading to potential read or write errors due to short channel lengths and gate-source/drain distances, which are approaching scaling limits.
Innovation Solution
A three-dimensional NOR flash memory structure is developed, featuring a pillar part with a conductive semiconductor material, charge accumulating parts, insulating parts, and control and selecting gates, allowing for active region formation without two-dimensional scale limitations and integration with a selecting transistor to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel length is shortened to improve integration, then degree of integration is improved, but reliability deteriorates due to unexpected breakdowns and read/write errors
Solution Approach 1:
The patent transitions from a planar two-dimensional memory cell layout to a three-dimensional structure by forming pillars vertically extending from the substrate. This vertical stacking allows memory cells to be arranged in multiple layers, significantly increasing integration density without further reducing the channel length and maintaining reliability through adequate spacing between cells.
Solution Approach 2:
The patent divides the continuous channel region into segmented pillars surrounded by insulating films. Each pillar is electrically isolated by insulating films formed on its surface, creating discrete memory cell units. This segmentation prevents electrical interference and unexpected breakdowns between adjacent cells, enhancing reliability while enabling higher integration.
2Productivity
If design rule is reduced to improve integration, then degree of integration is improved, but device complexity increases due to shorter gate-source/drain distances
Solution Approach 1:
The patent moves the memory cell structure into the vertical dimension by forming pillars that extend upward from the substrate. This allows the channel length to be defined by the pillar height rather than lateral dimensions, enabling integration improvement without further reducing the already minimal gate-source/drain distances in the planar direction, thus avoiding increased device complexity.
Solution Approach 2:
The patent implements a nested structure where insulating films are formed on the surface of each pillar, with charge accumulating films and control gates nested around the pillars. This nested arrangement efficiently packs multiple functional layers around the vertical channel, achieving high integration without complicating the gate-source/drain distance control.
3Productivity
If memory cell size is reduced to improve integration, then degree of integration is improved, but power consumption increases during programming
Solution Approach 1:
The patent forms memory cells with vertical pillars extending from the substrate, utilizing the vertical dimension to reduce the lateral footprint of each cell. This increases integration density without reducing the channel length or increasing programming power consumption, as the vertical structure maintains adequate electrical isolation and charge accumulation volume.
Solution Approach 2:
The patent employs a composite structure with pillars made of conductive semiconductor material surrounded by insulating films and charge accumulating films. This composite material approach enables compact cell design for high integration while the insulating films prevent leakage and the charge accumulating films efficiently store charges, maintaining low programming power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enables high integration and operating current while reducing power consumption during programming by forming memory cells in series with selecting transistors, thereby minimizing programming errors and optimizing memory cell performance.
Implementation Method 1
charges to the floating gate or trapped charges in a charge accumulation region are controlled so that a plurality of thresholds can be set for a memory cell
Implementation Method 2
a tunnel insulation layer, a charge accumulating layer, and a block insulation layer
Data Source
AI summary
A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present invention includes a pillar part, a charge accumulating part, an insulating part, a control gate and a selecting gate. The pillar part extends in a vertical direction from a surface of a substrate and includes a conductive semiconductor material. The charge accumulating part is formed by surrounding the pillar part. The insulating part is formed by surrounding the pillar part. The control gate is formed by surrounding the charge accumulating part. The selecting gate is formed by surrounding the insulating part. One end of the pillar part is electrically connected to a bit line via a contact hole and another one end of the pillar part is electrically connected to a conductive region formed on the surface of the substrate.