Memory Device Page Buffer Precharge Current Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices experience significant current and voltage drop phenomena during sense node precharge operations, which affect their performance and efficiency.
Innovation Solution
The memory device is designed with multiple page buffer groups connected to bit lines, where control logic controls the activation timings of these groups differently during sense node precharge operations, allowing for dualized and simultaneous precharge operations to improve current and voltage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all page buffers perform sense node precharge operation simultaneously, then the precharge operation is completed quickly, but current and voltage drops occur significantly
Solution Approach 1:
The patent divides page buffers into multiple groups (first page buffer group and second page buffer group) and performs sense node precharge operations in different time sequences. The first group performs precharge during a first time period while the second group performs precharge during a second time period, thereby segmenting the simultaneous operation into staggered operations that reduce current and voltage drops.
2Ease of operation
If page buffer groups are activated at the same time, then the operation is simple to control, but current consumption increases due to simultaneous precharge
Solution Approach 1:
The patent implements periodic action by activating different page buffer groups at different time periods. The control logic activates the first page buffer group during a first time period and the second page buffer group during a second time period, creating a time-division multiplexed operation that reduces peak current consumption while maintaining operational control.
Data Source
AI summary
The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block, a first page buffer group and a second page buffer group connected to bit lines of the memory block, and control logic configured to control the first page buffer group and the second page buffer group to perform a sense node precharge operation partially simultaneously.