Memory Region Programming for Threshold Voltage Convergence
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Solution Overview
Problem
Existing memory devices face challenges in optimizing storage efficiency and reliability, particularly in managing memory regions with varying levels of data integrity and usage, leading to inefficiencies in program operations and data retention.
Innovation Solution
Implementing a memory device with distinct memory regions that utilize different program voltage increments based on device states, where a first memory region uses a larger voltage difference for programming and a second region uses a smaller difference, enhancing threshold voltage convergence and read window margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform program voltage increment is used for all memory regions, then the programming process is simple, but data reliability and read window margins deteriorate in regions with high garbage data and program times
Solution Approach 1:
The patent divides the memory device into multiple memory regions (first memory region and second memory region) and applies different program voltage increments to each region based on its characteristics. The first memory region uses a first program voltage increment while the second memory region uses a second program voltage increment, allowing each region to be optimized for its specific workload and garbage data proportion.
Solution Approach 2:
The patent dynamically selects different program voltage increments based on the operational state of the memory device. When the memory device is in an activated state, it uses the first program voltage increment for programming operations. When in an idle state, it uses the second program voltage increment, allowing the system to adapt programming parameters to current operational conditions.
2Productivity
If a larger program voltage increment is used, then programming speed increases, but threshold voltage convergence and read window margins deteriorate
Solution Approach 1:
The patent applies different program voltage increments to different memory regions based on their specific characteristics and requirements. The first memory region uses a first program voltage increment optimized for its characteristics, while the second memory region uses a second program voltage increment, allowing each region to achieve optimal threshold voltage convergence for its specific workload.
Solution Approach 2:
The patent changes the program voltage increment parameter based on multiple factors including memory region characteristics, garbage data proportion, and operational state. By dynamically adjusting this critical parameter, the system optimizes both programming speed and threshold voltage convergence for different operating conditions.
3Reliability
If program operations are performed frequently in memory regions with high garbage data, then data retention improves, but programming efficiency and reliability deteriorate
Solution Approach 1:
The patent identifies memory regions with high garbage data proportions and applies specialized programming parameters to these regions. The first memory region, which contains faulty blocks and has high garbage data, uses a first program voltage increment that is optimized for maintaining data retention while managing programming efficiency in challenging conditions.
Solution Approach 2:
The patent performs preliminary identification and classification of memory regions based on their garbage data proportions and operational histories. This preliminary action allows the system to pre-configure appropriate programming parameters for each region, improving both data retention and programming efficiency before actual programming operations occur.
Data Source
AI summary
Examples of present disclosure disclose a memory device and an operation method thereof, and a readable storage medium. The memory device includes: a first memory region and a second memory region, each including a plurality of memory cells; and a peripheral circuit coupled with the first memory region and the second memory region and configured to: when writing data to the first memory region, perform a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually; and when writing data in the first memory region to the second memory region, perform a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually.