Recessed Vertical Memory Cell for Leakage and Data Retention
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Solution Overview
Problem
Existing memory devices face challenges in achieving higher integration, lower power consumption, and improved data retention characteristics due to reduced operating margins and decreased capacity of the floating body, particularly in miniaturized dynamic flash memories.
Innovation Solution
A memory device structure featuring a first semiconductor region with a recessed third semiconductor region and multiple impurity regions, utilizing a vertical cross-sectional design with controlled voltage application to manipulate threshold values and carrier operations, enabling efficient storage and erasure of data through impact ionization and gate-induced drain leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory device is miniaturized to achieve higher integration, then the density is improved, but the operating margin is reduced and data retention characteristics deteriorate
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical SGT (Surround Gate Transistor) architecture, moving the channel from horizontal to vertical orientation. This dimensional change enables higher integration density while maintaining reliable operation through enhanced gate control in the vertical configuration
Solution Approach 2:
The patent modifies the transistor structure parameters by introducing a recessed channel region and adjusting the gate electrode configuration in the vertical SGT architecture. These parameter changes enable improved carrier confinement and threshold voltage control, maintaining operating margins despite miniaturization
2Volume of moving object
If the floating body capacity is reduced due to miniaturization, then the device size is reduced, but the data retention characteristics worsen
Solution Approach 1:
The patent introduces a recessed channel region with specific doping characteristics localized in the vertical channel. This local structural modification enhances carrier confinement in the floating body region, improving data retention characteristics specifically in the miniaturized device without increasing overall device volume
Solution Approach 2:
By transitioning to vertical SGT architecture, the patent creates a three-dimensional floating body structure that provides enhanced carrier confinement volume efficiency. The vertical orientation allows better retention of stored carriers within the reduced device footprint
3Device complexity
If leakage current is not controlled, then the device operation is simpler, but the operating margin is reduced
Solution Approach 1:
The patent utilizes the impact ionization phenomenon, which normally generates leakage current, as a beneficial mechanism for carrier generation and storage. By controlling the vertical channel electric field, the device converts potential harmful leakage into useful carrier multiplication for data storage operations
Solution Approach 2:
The patent adjusts the vertical channel dimensions and doping parameters to optimize the balance between leakage current and useful carrier generation. The recessed channel structure modifies the electric field distribution to enhance desired operations while managing leakage effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances operating margin and density by reducing leakage current and increasing storage capacity, allowing for higher integration and efficient data retention in dynamic flash memories.
Implementation Method 1
a group of holes and a group of electrons generated by an impact ionization phenomenon within the channel by the source-drain current
Implementation Method 2
A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory
Data Source
AI summary
Provided is a memory semiconductor device including an access transistor, in which an n-type semiconductor layer is formed on a p-type semiconductor region provided on a substrate; a first p-type semiconductor layer that has a columnar shape exists in a vertical direction from a portion of the n-type semiconductor layer; an insulating layer that covers a portion of the first p-type semiconductor layer and a portion of the n-type semiconductor layer exists; in contact therewith, a first gate insulating layer contacts the first p-type semiconductor layer; in contact with the first gate insulating layer, a first gate conductive layer exists; a second p-type semiconductor layer whose surface is recessed exists on the first p-type semiconductor layer; a second gate insulating layer and a second gate conductive layer exist thereabove; and an n+ layer is provided on both sides thereof.