NAND Memory Multi-Programming Without Intervening Erase Cycles
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Solution Overview
Problem
Existing memory devices experience reduced lifespan due to program/erase (PE) cycle stress and time consumption, particularly in NAND memory, where intervening erase operations are time-consuming and contribute to wear-out, impacting performance and endurance.
Innovation Solution
Optimized control logic in memory sub-systems performs sequential programming without intervening erase operations by shifting data states to higher voltage levels, using firmware and memory device design to manage logical data states, allowing for multi-programming without intermediate erases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional program/erase cycles are used in NAND memory, then data can be stored and refreshed, but the memory device experiences increased wear and reduced lifespan
Solution Approach 1:
The patent extracts the erase operation from the conventional program/erase cycle, allowing programming operations to be performed without preceding or intervening erase operations. This separates the programming function from the erasing function, enabling data to be reprogrammed in the same physical block without requiring full block erasure, thereby reducing PE cycle stress on the memory device.
Solution Approach 2:
The patent changes the voltage state parameters of memory cells by shifting data states to higher voltage levels through sequential programming. Instead of returning cells to a ground state via erasure, the system progressively programs cells to increasingly higher voltage thresholds, maintaining functional data storage while avoiding the wear-inducing erase operation.
2Productivity
If intervening erase operations are performed between program operations, then memory blocks can be reused, but significant time is consumed and performance is reduced
Solution Approach 1:
The patent enables continuous programming operations by eliminating the interruptive erase step between program operations. Data can be sequentially programmed into the same physical block without interruption for erasure, maintaining continuous useful action (programming) while avoiding time-consuming erase operations, thereby improving overall productivity and reducing latency.
3Productivity
If multiple program operations are performed on the same memory block without erasing, then overhead time is reduced and performance improves, but control and management of data states becomes more complex
Solution Approach 1:
The patent introduces a voltage level dimension for managing data states, where data is organized by voltage thresholds rather than by physical block erasure cycles. By shifting data states to progressively higher voltage levels through sequential programming, the system adds a voltage-based organizational dimension that simplifies the management of multi-programmed data while maintaining programming efficiency.
Data Source
AI summary
A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic causes first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first voltage distribution programmed relative to a first threshold voltage (Vt) level. The control logic causes, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second voltage distribution programmed relative to a second Vt level, wherein the second Vt level is higher than the first Vt level.