3D NAND Weak Erase Pulse for Pillar Boosting Stress Release
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Solution Overview
Problem
In 3D NAND memory arrays, excess electrons trapped in pillars after array discharge cause a potential difference with local word lines, leading to pillar boosting that hinders data retention and increases latency and power consumption in conventional stress release methods.
Innovation Solution
Implementing a weak erase pulse (WEP) to discharge pillars using gate-induced drain leakage current, with controlled biases and pulse width, to release pillar boosting stress without increasing latency or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional approaches are used to release pillar boosting stress, then data retention is improved, but latency and power consumption increase
Solution Approach 1:
The patent applies parameter changes by modifying the voltage levels and pulse characteristics of the erase operation. Specifically, it uses a two-stage erase pulse approach: a first erase pulse at a first voltage level to initially discharge the pillar, followed by a second erase pulse at a second voltage level to complete the discharge. This staged parameter adjustment enables effective pillar boosting stress release while controlling latency and power consumption, resolving the contradiction between data retention improvement and time loss.
2Reliability
If conventional approaches are used to release pillar boosting stress, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent implements parameter changes by utilizing a two-stage voltage approach for erase pulses. The first erase pulse operates at a first voltage level to begin discharging the pillar, and the second erase pulse operates at a second voltage level to finish the discharge process. This staged parameter modification achieves effective pillar boosting stress release while optimizing power consumption, thereby resolving the contradiction between improving data retention and reducing energy use.
3Reliability
If excess electrons are trapped in pillars after array discharge, then potential difference is created, but data retention deteriorates due to pillar boosting
Solution Approach 1:
The patent applies the blessing in disguise principle by converting the harmful effect of trapped excess electrons in the pillar into a beneficial discharge process. By applying controlled erase pulses with specific voltage levels and timing, the harmful potential difference and pillar boosting effect are transformed into a controlled discharge mechanism that eliminates the harmful electrons and restores normal operation, thereby improving data retention.
Solution Approach 2:
The patent uses parameter changes by implementing a two-stage erase pulse sequence with different voltage levels. The first erase pulse at a first voltage level initiates the discharge of excess electrons from the pillar, and the second erase pulse at a second voltage level completes the discharge. This staged parameter adjustment effectively removes the harmful pillar boosting effect while maintaining control over the discharge process, resolving the contradiction between data retention and pillar boosting harm.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances data retention and reliability by efficiently discharging pillars, reducing read window budget loss and improving high-temperature data retention, while maintaining low power consumption and latency.
Implementation Method 1
Implementing a weak erase pulse (WEP) to discharge pillars using gate-induced drain leakage current
Data Source
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AI summary
Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.