Flash Memory Programming Compensation for Program Disturb
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Solution Overview
Problem
Flash memory devices suffer from program disturb, where unprogrammed memory cells experience threshold voltage changes due to voltage applications and coupling effects from adjacent cells, leading to read errors, and existing methods to mitigate this issue, such as using fixed pairs of programming pulses, result in increased programming time.
Innovation Solution
Implementing a method that counts potential CS2 situations, where adjacent bit lines have failed program verify operations, and applies compensation by generating double programming pulses or increasing the Vpass voltage on unselected word lines when the count exceeds a threshold, to prevent simultaneous programming of memory cells on either side of inhibited bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed number of pairs of programming pulses are used to reduce program disturb, then program disturb is reduced, but programming time increases
Solution Approach 1:
The patent implements a dynamic programming pulse generation method that adapts the programming scheme based on real-time verification results. Instead of using a fixed number of programming pulse pairs for all memory cells, the system dynamically determines whether to apply compensation programming pulses based on whether adjacent memory cells failed the program verify operation. This dynamic approach reduces programming time by avoiding unnecessary compensation pulses for cells that do not require them, while still reducing program disturb when needed.
Solution Approach 2:
The patent changes the programming parameters (number of programming pulse pairs) based on the verification status of adjacent memory cells. When adjacent cells fail verification, the system increases the number of programming pulse pairs applied to inhibited bit lines to compensate for capacitive coupling effects. This parameter adjustment resolves the contradiction by applying additional programming pulses only when necessary, rather than uniformly to all cells, thus reducing overall programming time while maintaining program disturb reduction where needed.
2Reliability
If double programming pulses are generated for each word line during middle range programming, then program disturb is reduced, but device complexity increases
Solution Approach 1:
The patent applies different programming strategies to different spatial locations (bit lines) based on local conditions. Specifically, when a memory cell on one bit line fails verification, the system applies compensation programming pulses only to the adjacent inhibited bit lines that are susceptible to program disturb, rather than uniformly to all bit lines. This localized approach reduces program disturb where needed while minimizing the overall complexity of the programming control system.
Solution Approach 2:
The patent segments the programming operation into distinct phases: normal programming pulses, program verify operations, and conditional compensation programming pulses. By dividing the programming process into these segments and applying compensation pulses only in specific circumstances (when adjacent cells fail verification), the system reduces program disturb without requiring complex continuous control mechanisms throughout the entire programming sequence.
3Productivity
If programming pulses are applied to adjacent bit lines simultaneously, then programming speed is improved, but program disturb increases
Solution Approach 1:
The patent implements preliminary anti-action by performing program verify operations after each programming pulse and proactively applying compensation programming pulses to inhibited bit lines when adjacent cells fail verification. This preventive measure counteracts the capacitive coupling effects that would otherwise cause program disturb, allowing the system to maintain high programming speed through parallel bit line programming while preventing the harmful threshold voltage shifts in inhibited cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces program disturb by compensating for potential CS2 situations through adjusted programming pulses and voltages, thereby minimizing read errors and reducing programming time.
Implementation Method 1
Changes in threshold voltage of the memory cells, through programming of charge storage structures (e.g., floating gates or charge traps)
Implementation Method 2
the adjacent series strings of memory cells, on either side of the inhibited series string, can affect the threshold voltages of the inhibited memory cells by floating gate-to-floating gate capacitive coupling between memory cells
Data Source
AI summary
Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.