Nonvolatile Memory Programming Verification Optimization

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Solution Overview

Problem

Current nonvolatile memory devices face challenges in reducing program verification time, which is essential for efficient data storage and retrieval, especially in high-capacity and low-power applications like SSDs and smartphones.

Innovation Solution

A method and device for programming nonvolatile memory devices that involves applying a program voltage and verification voltage to memory cells, sensing their states, and selecting target cells based on the sensing results, with data latches reordered into sequential binary code to optimize the verification process, reducing the number of dumping operations and improving programming speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple program loops are executed to store multiple data bits at a memory cell with verification operation for each program state, then programming reliability is improved, but program verification time increases

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidprogram verification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-charging bit lines before verification operations. The control circuit pre-charges bit lines to a first voltage level before sensing operations, and to a second voltage level before verification operations. This preliminary preparation eliminates the need for time-consuming in-place charging during verification, significantly reducing verification time while maintaining programming reliability through systematic voltage application at each program loop.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If traditional verification methods are used without data latch reordering, then device complexity is lower, but programming speed is reduced due to multiple dumping operations

Engineering Contradiction:
Improveprogramming speedVSAvoiddata latch reordering complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamics by dynamically reordering data latches into sequential binary code format during the programming process. The control circuit adapts the data latch configuration based on the current program state, transforming static data storage into a dynamic structure that optimizes verification efficiency. This dynamic reordering reduces the number of dumping operations required, thereby increasing programming speed despite the added control complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9349482B2Nonvolatile memory device and operating method thereof
Publication Date: 2016.05.24 SAMSUNG ELECTRONICS CO LTD
  • US9349482B2 patent drawing
  • US9349482B2 patent drawing
  • US9349482B2 patent drawing

AI summary

A method of programming a nonvolatile memory device is provided which includes applying a program voltage to selected ones of a plurality of memory cells; applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied; sensing the memory cells to which the selected verification voltage is applied; selecting memory cells programmed to a target state referring to the sensing result and target state data; and determining whether programming of the selected memory cells is passed or failed.