3D Memory Stair-Step Layout for Reliable Vertical Access Lines
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently forming memory circuitry, particularly in creating reliable and efficient connections between vertically-stacked memory cells and access lines, which affects data storage and retrieval performance.
Innovation Solution
The method involves forming memory arrays with vertically-alternating insulative and conductive tiers, using stair-step structures to create direct electrical connections between memory cells and access lines, and employing gate-last or gate-first processing to enhance the integration of memory cells and peripheral circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically-stacked memory cells are formed with conventional connection structures, then manufacturing complexity increases, but electrical connection reliability between memory cells and access lines deteriorates
Solution Approach 1:
The access lines are segmented into multiple portions (first portion, second portion, third portion) that are positioned at different vertical levels. This segmentation allows each portion to connect to memory cells at corresponding heights, simplifying the manufacturing process by enabling staged formation of connections rather than requiring complex through-stack routing.
Solution Approach 2:
The patent transitions from planar connections to three-dimensional stacked connections by positioning access line portions at different vertical levels (z-dimension). The first access line portion connects to memory cells at a lower level, the second portion at an intermediate level, and the third portion at a higher level, creating a vertical stacking architecture that improves electrical connection reliability while managing manufacturing complexity through dimensional organization.
2Productivity
If access lines are positioned at multiple vertical levels, then electrical connection efficiency improves, but manufacturing process complexity increases
Solution Approach 1:
The access lines are formed in a predetermined stacked arrangement before memory cells are fully integrated. The first, second, and third access line portions are positioned at their respective vertical levels in advance, establishing the electrical connection framework prior to final memory cell assembly. This preliminary structuring enables efficient data retrieval while simplifying subsequent manufacturing steps.
Data Source
AI summary
Memory circuitry comprising strings of memory cells comprises channel-material strings of memory cells extending through insulative tiers and conductive tiers in a memory-array region. The insulative and conductive tiers extend from the memory-array region into a stair-step region. A plurality of stair-step structures is in the stair-step region. The stair-step structures individually comprise two opposing flights of stairs. The stair-step structures comprise an SGD stair-step structure and non-SGD stair-step structures. At least one of the non-SGD stair-step structures has less total stairs than are in individual of multiple others of the non-SGD stair-step structures. Other embodiments, including method, are disclosed.