Memory Read Control Using Adjacent Word Line Interference Correction
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Solution Overview
Problem
Existing memory systems face challenges in accurately reading data due to interference between memory cells, leading to incorrect decoding and errors in data retrieval, particularly in multi-level cell configurations like TLC, MLC, QLC, and PLC, where adjacent threshold voltage distributions overlap, causing misinterpretation of data states.
Innovation Solution
The memory system employs a memory controller that acquires data from selected cells and adjacent cells to correct threshold voltage shifts through soft bit decoding, utilizing error correction circuits to generate accurate read data by considering interference effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If soft bit decoding processing is performed using data from selected cells and adjacent cells to correct threshold voltage shifts, then data reading accuracy is improved, but processing time and computational complexity increase
Solution Approach 1:
The patent performs preliminary reading of adjacent cell data before using it to correct the selected cell data. The memory controller reads data from adjacent cells (WL-1 and WL+1) first, then uses this information to correct threshold voltage shifts in the selected cell (WL) through soft bit decoding. This preliminary action allows the system to prepare correction data in advance, improving accuracy while managing processing time through staged operations.
2Reliability
If multiple adjacent word lines are read to correct interference effects, then data retrieval reliability is improved, but memory access time increases
Solution Approach 1:
The patent merges the reading operations of the selected word line and adjacent word lines into a coordinated process. The memory controller simultaneously manages reading from WL-1, WL, and WL+1, combining their data to perform interference correction. By merging these operations and using the adjacent cell data collectively for soft bit decoding, the system improves retrieval reliability while minimizing the total access time through efficient resource utilization.
3Measurement precision
If correction data from adjacent cells is applied to mitigate interference, then decoding accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where data from adjacent cells is used to generate correction information that is fed back into the decoding process for the selected cell. The memory controller reads adjacent cell data, processes it to determine interference effects, and applies corrections to the selected cell data through soft bit decoding. This feedback loop continuously improves decoding accuracy by using actual measured interference patterns to adjust the decoding process.
Data Source
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AI summary
According to one embodiment, a system (1) includes: a memory device including word lines and memory cells (MC0 to MCn-1) connected to word lines (WL0 to WLn-1); and a memory controller(10) , the memory controller acquires first data (DX1, DX2, DX3) related to threshold voltages of selected cells connected to a selected word line among the word lines, acquires second data (RD1L, RD1M, RD1U) from first adjacent cells connected to a first adjacent word line adjacent to one end of the selected word line, acquires first correction data (DY1, DY2, DY3) by correcting the first data based on the second data, acquires third data (RD2L, RD2M, RD2U) from second adjacent cells connected to a second adjacent word line adjacent to another end of the selected word line, acquires second correction data (DZ1, DZ2, DZ3) by correcting the first correction data based on the third data, and executes soft bit decoding processing on the second correction data to generate read data from the selected cells.