Dual-Gate Semiconductor Memory Cell for Low-Leakage Fuse Reading
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Solution Overview
Problem
Memory devices with metal fuses have large dimensions due to large transistors handling large currents, leading to significant leakage current that deteriorates data access accuracy.
Innovation Solution
Implementing power-gate and cascode-gate transistors in semiconductor devices to reduce the number of transistors and minimize leakage current, thereby reducing device area and enhancing data access accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large transistors are used to handle large currents for metal fuse, then the current handling capability is improved, but the device area increases
Solution Approach 1:
The transistor gate is divided into two independent gates: a front gate for standard transistor operation and a back gate for leakage control. This segmentation allows the transistor to function as a normal transistor for current handling while independently controlling leakage current through the back gate, thereby reducing the required transistor size and device area while maintaining current handling capability
Solution Approach 2:
The invention changes the electrical parameters of the transistor by applying different voltages to the back gate. By adjusting the back gate voltage, the transistor can operate in different modes (enhancement mode for current handling, depletion mode for leakage reduction), enabling the same transistor structure to serve multiple functions with optimized size
2Power
If large transistors are used to handle large currents for metal fuse, then the current handling capability is improved, but the leakage current increases
Solution Approach 1:
The transistor gate is divided into two independent gates: a front gate for standard transistor operation and a back gate for leakage control. This segmentation allows the transistor to function as a normal transistor for current handling while independently controlling leakage current through the back gate, thereby reducing the required transistor size and device area while maintaining current handling capability
Solution Approach 2:
The back gate acts as an intermediary control element that mediates between the front gate's current handling function and the leakage current issue. By applying appropriate voltages to the back gate, it actively suppresses leakage current while allowing the front gate to maintain full current handling capability
3Area of stationary object
If the number of transistors is reduced, then the device area is reduced, but the leakage current control capability may be compromised
Solution Approach 1:
The transistor gate is divided into two independent gates: a front gate for standard transistor operation and a back gate for leakage control. This segmentation allows the transistor to function as a normal transistor for current handling while independently controlling leakage current through the back gate, thereby reducing the required transistor size and device area while maintaining current handling capability
Solution Approach 2:
The dual-gate transistor structure provides multi-functionality: the same transistor can simultaneously perform current handling, leakage control, and data storage functions. This universality allows reduction in the number of transistors needed in the memory device while maintaining or even improving leakage control capability through the back gate's active control
Data Source
AI summary
A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes a first transistor, the second transistor, a first circuit, a second circuit and a third transistor. The second transistor is electrically connected to the first transistor, wherein gates of the first transistor and the second transistor are electrically connected to a word line. The first circuit is electrically connected between a drain of the first transistor and a first bit line. The second circuit is electrically connected between a drain of the second transistor and a second bit line. The third transistor is electrically connected between the drain of the first transistor and the drain of the second transistor.