Semiconductor Integrated Circuit Bit Line Voltage Selection
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Solution Overview
Problem
The quick-pass write method for semiconductor integrated circuits requires two stages of bit line charging, leading to longer charging times and inefficiencies in programming speed and threshold voltage distribution.
Innovation Solution
A semiconductor integrated circuit device with a data circuit that selects and applies different voltages to bit lines based on program data, allowing for simultaneous strong and weak programming without two-stage charging, thereby reducing charging time and improving programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-stage bit line charging (VDD charging followed by 0.5 V charging) is used in the quick-pass write method, then narrow threshold voltage distribution is achieved, but the bit line charging time becomes long
Solution Approach 1:
The patent segments the bit line charging operation into multiple independent voltage levels (VDD, 0.5V, 0V) that can be simultaneously applied to different bit lines. The charging control circuit divides the bit lines into multiple groups and applies appropriate voltages to each group in parallel, eliminating the sequential two-stage charging process while maintaining narrow threshold voltage distribution.
Solution Approach 2:
The patent implements dynamic voltage selection where the charging control circuit dynamically determines the appropriate voltage level for each bit line based on the programming requirements. The circuit dynamically switches between different voltage levels (VDD, 0.5V, 0V) and simultaneously applies them to different bit lines, enabling adaptive charging that maintains precision while reducing time.
2Manufacturing precision
If two-stage charging operation is performed to program memory cells with different voltage requirements, then programming precision is improved, but programming speed is reduced
Solution Approach 1:
The patent segments the memory cell array into multiple regions that can be programmed simultaneously with different voltage levels. The charging control circuit divides bit lines into multiple groups and applies VDD, 0.5V, or 0V to different groups in parallel, enabling precise programming of multiple memory cells simultaneously without requiring sequential two-stage operations.
Solution Approach 2:
The patent enables continuous programming operation by eliminating the idle time between VDD charging and 0.5V charging stages. The charging control circuit continuously applies appropriate voltages to different bit lines throughout the programming process, ensuring that useful programming action occurs without interruption or waiting periods.
Data Source
AI summary
A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data to be programmed into a memory cell and changes the data held according to a verify result from the memory cell. Then, the data circuit selects one of the bit line application voltage terminals based on the data held therein and applies voltage of the selected bit line application voltage terminal to a bit line BLe or BLo.