Segmented Source Plates for Compact Memory Sub-Block Access
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Solution Overview
Problem
Existing memory devices face challenges in achieving reliable sub-block access due to the use of physically segregated select gate devices, which increase complexity, size, and cost, and result in threshold voltage variations leading to performance issues.
Innovation Solution
Implementing segmented source plates in memory devices, where each sub-block has a separate source segment, and using non-segregated logical select gate layers at the drain-side, allowing precise control of threshold voltages through individual source voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If physically segregated select gate devices are used for sub-block access, then sub-block selection capability is achieved, but device complexity and size increase
Solution Approach 1:
The source plate is divided into multiple independent source segments, with each segment corresponding to a specific sub-block. This segmentation allows selective activation of individual sub-blocks through independent source segment control, eliminating the need for physically segregated select gate devices while maintaining sub-block selection capability.
Solution Approach 2:
The patent extracts the selection function from separate physical select gate devices and integrates it into the source plate structure itself. By making the source plate segments selectively controllable, the selection capability is embedded directly in the source structure, reducing overall device complexity.
2Adaptability or versatility
If physically segregated select gate devices are used for sub-block access, then sub-block selection capability is achieved, but threshold voltage variations increase
Solution Approach 1:
The patent merges the source plate structure with the selection function, creating an integrated source-plate-selector system. This unification ensures that all memory cells within a sub-block share the same reference potential when that sub-block is selected, eliminating threshold voltage variations caused by physically segregated select gate devices.
Solution Approach 2:
Each source segment is independently controllable and provides a localized reference potential specific to its corresponding sub-block. This local control ensures uniform threshold voltage characteristics within each sub-block while maintaining the ability to selectively access individual sub-blocks.
3Adaptability or versatility
If physically segregated select gate devices are used for sub-block access, then sub-block selection capability is achieved, but manufacturing cost increases
Solution Approach 1:
The source plate structure serves multiple functions: it provides the reference potential for memory cell operations and simultaneously acts as the selection mechanism for different sub-blocks. This multi-functionality eliminates the need for separate select gate devices, reducing manufacturing complexity and cost while maintaining sub-block selection capability.
4Adaptability or versatility
If physically segregated select gate devices are used for sub-block access, then sub-block selection capability is achieved, but physical spacing between sub-blocks increases
Solution Approach 1:
The source plate is segmented into independent regions that can be electrically isolated through cuts or gaps. This segmentation allows compact arrangement of sub-blocks without requiring large spacing for physical select gate devices, as the electrical isolation is achieved through the source plate structure itself.
Solution Approach 2:
The patent transitions from a planar arrangement requiring lateral spacing for select gate devices to a vertical integration where source plate segments are stacked or arranged in layers. This dimensional change allows sub-blocks to be positioned closer together while maintaining independent selection capability through the segmented source structure.
Data Source
AI summary
Control logic in a memory device causes a plurality of source control signals to be applied to a plurality of deintegrated source segments of a first block of a plurality of blocks of a memory array of a memory device to selectively activate a plurality of sub-blocks of the first block and programs a plurality of select gate devices in a plurality of logical select gate layers spanning the plurality of sub-blocks and positioned at a drain-side of the first block of the memory array with a threshold voltage pattern.


