Voltage Generation Circuit Layout Area Reduction
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Solution Overview
Problem
Existing voltage generation circuits in semiconductor memory devices, such as NAND flash memory, face challenges in efficiently generating high voltages for write and erase operations while preventing simultaneous generation of program and erase voltages and ensuring accurate detection of these voltages without increasing layout area.
Innovation Solution
A voltage generation circuit comprising a first boost circuit, output circuits, a rectifying circuit, and a detection circuit, where the detection circuit is connected only to the charge pump circuit, and local pump circuits are used to generate program and erase voltages separately, with pump enable signals controlling their operation to prevent simultaneous generation and detection, thereby reducing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate detection circuits are provided for program voltage and erase voltage, then voltage detection accuracy is improved, but layout area increases
Solution Approach 1:
The detection circuit is designed to serve multiple functions by detecting both program voltage and erase voltage using a single circuit. The circuit selectively detects different voltages based on control signals, eliminating the need for separate detection circuits for each voltage type while maintaining detection accuracy.
Solution Approach 2:
The detection circuit's functionality is made dynamic through control signals that enable it to switch between detecting program voltage and erase voltage. This dynamic reconfiguration allows one circuit to perform multiple detection tasks at different times, reducing the overall number of detection circuits needed.
2Speed
If program and erase voltages are generated simultaneously, then operational speed is improved, but harmful factors increase due to simultaneous high voltage generation
Solution Approach 1:
The generation of program and erase voltages is organized into periodic cycles with clear temporal separation. The control circuit generates pump enable signals that activate the charge pump circuit at specific intervals, ensuring that program and erase operations occur in alternating periods rather than simultaneously, thus preventing harmful interactions.
Solution Approach 2:
The control circuit acts as an intermediary that manages the timing and activation of voltage generation. It uses pump enable signals to coordinate the charge pump circuit's operation, ensuring that program and erase voltages are generated at appropriate times without overlapping, thereby preventing simultaneous high voltage generation while maintaining operational efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively generates high voltages for write and erase operations while ensuring that program and erase voltages are not generated simultaneously, allowing for efficient voltage detection without the need for multiple detection circuits, thus reducing the layout area and improving operational efficiency.
Implementation Method 1
A NAND flash memory uses high voltages which are higher than an external power supply voltage at times of write and erase. These high voltages are generated by using a charge pump circuit functioning as a boost circuit.
Implementation Method 2
An output voltage of the charge pump circuit is detected by a detection circuit, and the operation of the charge pump circuit is controlled based on an output signal of the detection circuit.
Data Source
AI summary
According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes. The first output circuit is connected to the first boost circuit, and outputs the first voltage as a second voltage in the first operation mode. The rectifying circuit is connected to the first boost circuit, and outputs a third voltage which is lower than the first voltage in the first operation mode. The second output circuit short-circuits the rectifying circuit in the second operation mode, and outputs the first voltage as a fourth voltage. The detection circuit detects the second and fourth voltages which are supplied from the first and second output circuits.