Three-Gate Flash Memory Cell Array With Vertical Gate Line Reorientation
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Solution Overview
Problem
Existing split gate non-volatile memory cell arrays cannot perform true single bit operation independently without interfering with adjacent memory cells during programming, reading, and erasing.
Innovation Solution
The reorientation of program-erase gate lines, source lines, and select gate lines in a 3-gate memory cell array from horizontal to vertical configurations allows for individual programming, reading, and erasing of each memory cell without affecting adjacent cells, enabling true single bit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in rows and columns with shared source lines, bit lines, select gate lines, and PE gate lines, then the array structure is compact and manufacturable, but individual memory cell operation interferes with adjacent cells during programming, reading, and erasing
Solution Approach 1:
The patent divides the gate control into three independent segments: select gate lines for row selection, PE gate lines for column selection, and source line voltage control. This segmentation allows independent addressing of individual memory cells by activating specific combinations of select gates and source lines, preventing interference with adjacent cells while maintaining array density.
Solution Approach 2:
The patent introduces a third dimension of control by using source line voltage states (selected vs. unselected voltages) in addition to the traditional row and column gate selections. This dimensional addition enables precise single cell addressing by requiring three simultaneous conditions: selected select gate, selected PE gate, and selected source line voltage, thereby isolating individual cell operations from adjacent cells.
2Ease of manufacture
If PE gate lines are configured horizontally to connect PE gates of memory cell pairs, then manufacturing is simplified, but erasure operations affect all cells in the row rather than individual cells
Solution Approach 1:
The patent segments the PE gate control by associating each PE gate with a specific column rather than sharing horizontal PE gate lines across rows. Each PE gate line now controls only the PE gates in its column, allowing independent column selection. This segmentation enables individual cell erasure by combining specific select gate row selections with specific PE gate column selections.
Solution Approach 2:
The patent changes the PE gate line configuration from horizontal (row-based) to vertical (column-based), adding a dimensional reorientation that enables independent column control. This dimensional change allows the PE gate lines to work in conjunction with select gate lines to address individual cells, transforming the erasure operation from row-wide to cell-specific.
3Ease of operation
If select gates control channel conductivity for reading, then read operation is enabled, but programming and erasing operations cannot be performed independently on individual cells
Solution Approach 1:
The patent makes the select gate and PE gate combinations universal for all three operations (programming, reading, and erasing). The same pair of selected gates can perform any operation by changing the voltage applied to the source line and the gate voltages, eliminating the need for separate control mechanisms for each operation type and enabling independent cell manipulation.
Solution Approach 2:
The patent introduces dynamic voltage control to the source line, where the source line voltage can be switched between selected state (enabling current flow for read) and unselected state (enabling programming or erasing). This dynamic voltage modulation allows the same hardware configuration to adapt to different operations, providing independent program-read-erase capability on individual cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables independent operation of each memory cell, preventing interference and ensuring accurate programming, reading, and erasing of single bits within the array.
Implementation Method 1
A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18
Implementation Method 2
electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the PE gate 30 via Fowler-Nordheim tunneling
Implementation Method 3
Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20
Data Source
AI summary
A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.