Flash Memory Erase Verification Voltage for Cycling Degradation
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Solution Overview
Problem
NAND-type flash memory apparatuses face challenges in achieving a balance between program interference and cycling degradation due to inappropriate setting of erase verification voltage, which worsens with increasing program/erase cycling.
Innovation Solution
A flash memory apparatus and method that dynamically adjusts the erase verification voltage based on the current pulse count value required for erase verification, recording changes in pulse count and adjusting the voltage to mitigate interference and degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the erase verification voltage is set too high, then program interference is reduced, but cycling degradation worsens
Solution Approach 1:
The patent applies dynamics by making the erase verification voltage adjustable rather than fixed. The voltage is dynamically changed based on the number of program/erase cycling operations performed. In early stages, a higher voltage is used to minimize program interference, while in later stages, the voltage is reduced to minimize cycling degradation, thus resolving the contradiction between these two harmful factors
Solution Approach 2:
The patent changes the parameter of erase verification voltage based on the cycling stage. By monitoring the number of program/erase cycling operations and adjusting the voltage parameter accordingly, the system adapts to different operational conditions. This parameter change allows the system to optimize performance at each stage, reducing both program interference and cycling degradation
2Reliability
If the erase verification voltage is set too low, then cycling degradation is reduced, but program interference worsens
Solution Approach 1:
The system dynamically adjusts the erase verification voltage based on the current cycling stage. Rather than using a fixed low voltage that causes program interference in early stages, the system starts with a higher voltage and gradually reduces it as cycling progresses, thereby minimizing both program interference and cycling degradation at appropriate times
Solution Approach 2:
The patent implements parameter changes by modifying the erase verification voltage based on the number of program/erase cycling operations. This dynamic parameter adjustment ensures that the voltage is optimized for each cycling stage, preventing program interference when needed and reducing cycling degradation when appropriate
3Device complexity
If a fixed erase verification voltage is used, then device complexity is reduced, but adaptability to different cycling stages worsens
Solution Approach 1:
The patent introduces a dynamic control mechanism that adjusts the erase verification voltage based on the number of program/erase cycling operations. This dynamic approach, while increasing some control complexity, provides significant adaptability to different cycling stages, allowing the system to optimize performance throughout the product's lifecycle
Solution Approach 2:
The system incorporates feedback by monitoring the number of program/erase cycling operations and using this information to adjust the erase verification voltage. This feedback mechanism enables the system to adapt to changing conditions and optimize performance at each cycling stage, justifying the additional control complexity
Data Source
AI summary
A flash memory apparatus and an erasing method thereof are provided. The erasing method includes the following steps. Memory blocks are operated according to an operation command. After any one of the memory blocks undergoes a program/erase cycling, whether an accumulated cycle count of the program/erase cycling of the any one of the memory blocks reaches one of multiple interruption points is determined. When the cycle count of the any one of the memory blocks reaches the one of the interruption points, a current pulse count value of a step pulse required for the any one of the memory blocks to pass an erase verification during the program/erase cycling is recorded. An erase verification voltage for the erase verification is adjusted according to the current pulse count value.