3D ESD Diode Structure for High Current and Low Capacitance
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Solution Overview
Problem
Semiconductor devices face challenges in integrating electrostatic discharge (ESD) diodes with high current drivability and reduced capacitance to protect against static electricity, which can lead to increased area requirements and decreased signal integrity due to the need for multiple impurity regions and metal lines.
Innovation Solution
The semiconductor device incorporates ESD diodes with impurity regions having uneven surfaces, specifically a first impurity region doped with N-type impurities and a second impurity region doped with P-type impurities, connected between power supply pads and signal pads, to enhance current drivability while maintaining a compact design and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple impurity regions and metal lines are used to achieve high current drivability, then the ESD diode can provide adequate protection, but the area requirement increases and degree of integration decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by forming impurity regions that extend in the depth direction (third direction) perpendicular to the substrate surface. This vertical extension allows the ESD diode to achieve high current drivability through increased junction area in the depth dimension, thereby reducing the required surface area and improving degree of integration.
Solution Approach 2:
The patent divides the impurity regions into multiple segments extending vertically, with first impurity regions and second impurity regions alternating in the depth direction. This segmentation creates multiple junction surfaces that collectively provide high current drivability while compacting the structure vertically, thus reducing the horizontal area requirement.
2Reliability
If multiple metal lines are used to connect impurity regions, then the ESD diode structure is more robust, but the capacitance increases and signal integrity deteriorates
Solution Approach 1:
The patent merges multiple impurity regions of the same conductivity type into vertically extended continuous regions, reducing the number of separate metal line connections required. By combining first impurity regions and second impurity regions into vertically integrated structures, the patent reduces the total capacitance associated with multiple discrete metal line connections while maintaining structural robustness through the extended vertical geometry.
3Area of stationary object
If the ESD diode area is reduced to improve degree of integration, then more devices can be integrated, but the current drivability decreases
Solution Approach 1:
The patent compensates for reduced surface area by extending impurity regions vertically in the depth direction, creating a three-dimensional structure where the junction area is increased through depth rather than surface expansion. This allows the ESD diode to maintain high current drivability while occupying less surface area, thereby improving degree of integration.
Solution Approach 2:
The patent changes the geometric parameters of the impurity regions by extending them in the depth direction and creating alternating patterns of first and second impurity regions. This parameter change transforms the structure from a shallow wide configuration to a deep compact configuration, achieving high current drivability in a reduced surface footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high current drivability in a limited area, improving the degree of integration and signal integrity by reducing the number of metal lines and capacitance, thus effectively protecting the semiconductor device from static electricity without compromising performance.
Implementation Method 1
a lower surface of at least one of the first impurity region and the second impurity region has an uneven structure
Implementation Method 2
a first impurity region doped with impurities of a first conductivity type and connected to the first power supply pad, and a second impurity region doped with impurities of a second conductivity type different from the first conductivity type and connected to the signal pad
Data Source
AI summary
A semiconductor device according to an embodiment of the present inventive concept comprises: a first power supply pad configured to receive a first power supply voltage; a second power supply pad configured to receive a second power supply voltage, the second power supply voltage having a level lower than a level of the first power supply voltage; a signal pad configured to exchange a signal; and a first electrostatic discharge (ESD) diode comprising a first impurity region doped with impurities of a first conductivity type and connected to the first power supply pad, and a second impurity region doped with impurities of a second conductivity type different from the first conductivity type and connected to the signal pad, wherein a lower surface of at least one of the first impurity region and the second impurity region has an uneven structure.