Solid-State Devices TRIZ Cases

A through-via and film layout separates active and peripheral regions to raise light extraction while reducing mura risk and process cost.

Linear separation detaches the wafer from the donor by X-axis wafer movement, reducing LED transfer defects, distortion, and misalignment.

Embedding the PAD electrode around a smaller logic substrate frees circuit area, shortens wiring, and lowers parasitic capacitance.

A deep vertical transfer gate and highly doped charge collection area shrink pixel pitch while preserving charge transfer in image sensors.

Offset apertures in the light-shielding layer suppress large-angle light exitance, reducing color deviation while preserving fingerprint sensing.

Through holes segment overlapping power and data lines in display panels to cut parasitic capacitance and reduce signal crosstalk.

Corner fixing parts free more central opening space for optical components while preserving lens-to-holder sealing in a compact photoelectric sensor.

Transfer control circuits swap pseudo-channel commands and data words to reduce skew and preserve bandwidth in stacked chips.

Diffractive trenches and low-index layers extend the light path in a silicon photodiode, boosting near-IR quantum efficiency.

Partially overlapping microlenses compress broad micro-LED emission into the acceptance cone, improving light coupling in ultra-dense displays.

Press-molded silica glass combines a hermetic UV LED seal and lens to improve UV transmittance, light extraction, and package durability.

A dual-through-via display layout improves light extraction while preserving bonding pad access through passivation and film layers.

A gate electrode overlapping the drain raises threshold voltage, stabilizing diode-based static electricity discharge in display circuits.

A recessed bond pad with low-strain oxide and nitride layers plus CMP reduces substrate bowing and improves photolithography precision.

Peripheral carrier absorbing regions around pads and wiring block stray light and carriers, improving avalanche photodiode detection accuracy.

A repeating PG-aligned cell layout overlaps metallization segments to preserve routability, electrical continuity, and dense area utilization.

Diels-Alder functionalization tunes polyurethane pad zeta potential and abrasive affinity across slurry pH to raise CMP rates and cut defects.

Isolation regions and central voltage control improve sub-pixel signal separation and electron transfer for more accurate distance measurement.

Selective dielectric removal limits lateral oxide encroachment, keeping tunnel dielectric thickness uniform for stable embedded flash thresholds.

A diffusion-blocking layer and oxide cap suppress interdiffusion in MTJ memory elements, improving annealing stability and MRAM endurance.

Series-connected MFM decoupling capacitors split input voltage to limit dielectric stress and integrate with FeRAM fabrication to save area and cost.

Controlled dry etching through stacked insulating and color resist layers limits metal oxidation at pixel vias and lowers contact resistance.

A carrier-confining doping layout cuts dark current while sustaining avalanche gain and low leakage in direct time-of-flight sensing.

A varying-thickness dielectric with metal grid and light shield improves small-pixel light sensitivity while reducing optical and electrical crosstalk.

Event-driven SRAM bins under SPAD pixels replace bulky counters, cutting ToF sensor power while preserving small-pitch resolution and frame rate.

Grooves, a reflective light-shielding layer, and an air gap limit cross-lighting between adjacent emitters to improve on/off luminance contrast.

Discontinuous optical isolation around LED pixels cuts photon spillage and boosts contrast without sacrificing light output.

An electric conductor between dual column signal lines suppresses parasitic-capacitance crosstalk while enabling parallel pixel readout.

Scattering optics, light blocking layers, and optical adhesive reduce splice-line visibility while simplifying large-format LED display assembly.

Identical pixel structures with switchable vertical transfer gates unify image and depth sensing while easing substrate integration and cutting power use.

Peripheral metal wires are thickened while display-area lines stay thinner to lower resistance for high-frequency signals and reduce short-circuit risk.

Uneven impurity-region surfaces boost ESD current handling in less area while cutting metal-line count and capacitance for better signal integrity.

On-chip lenses and shallow intra-pixel grooves balance same-color pixel sensitivity in Bayer CMOS sensors for more uniform image capture.

Vertical vias through a memory die shorten sensor-to-logic signal paths, cutting energy use and easing sensor die fabrication.

A two-layer protruding separator preserves pixel hydrophobicity and guides inkjet emission layers for higher-resolution OLED fabrication.

Mirror-polished dummy wafers block oxygen diffusion during Ar annealing, reducing LPDs on bonded SOI wafers with backside oxide films.

Capacitors built in redundant substrate areas free device area while maintaining accurate capacitance and process-compatible integration.

Patterned recesses beside the chip-receiving area vent gas during laser lift-off, improving micro LED transfer alignment, rate, and yield.

Two-directional metal routing lets modular ESD power clamp cells fit irregular chip blank areas without redesign or manual placement.

An uneven impurity-junction ESD diode boosts current handling in limited chip area while lowering capacitance and preserving signal integrity.

Thermal eutectic self-alignment keeps adhesive layers more uniform across multiple LEDs, reducing color unevenness and heat resistance variation.

A trench between the photodiode and charge retention region strengthens pinning to curb dark current and white spots in back-illuminated CMOS sensors.

Recessed and projecting groove sidewalls diffuse and attenuate reflected light, reducing flare in the pixel region and improving image quality.

Stacked and folded planar capacitors cut parasitic coupling and charge disturbance, improving non-volatile memory retention and endurance.

Hydrophilic and hydrophobic insulating regions self-position light-emitting elements between electrodes, improving pixel alignment without barriers.

Fixed-charge films lining and sealing sensor grooves create internal voids that raise reflection and curb optical color mixing and blooming.

A radial shared-pixel layout places floating diffusion and readout transistors to shrink CMOS pixels while limiting capacitance, noise, and charge mixing.

A stepped through-hole with linked first and second grooves lowers source/drain climbing height and prevents side-wall breakage in OLED array substrates.

Different silicide contacts for p-type and n-type source/drain regions improve high-temperature conductivity and transistor robustness.

Vertical support structures aligned to staircase contacts improve word line replacement control and expand contact landing space in 3D memory.

Convex insulating structures hold and electrically align micro LEDs, improving placement, luminance, durability, and pixel density.

Refractive-index and bandgap tuning across quantum well and barrier layers cuts backside reflection and boosts 900-1000 nm light output.

A staged transfer-column layout creates a potential gradient that shortens pixel-to-transfer distance and improves charge transfer efficiency.

Buffered frame division and synchronized data input/output prevent tearing in rotating POV displays, improving smooth image rendering.

Differential etching of alternating sacrificial layers forms a wavy electrode that raises memory cell capacitance without excessive structure complexity.

Segmented adhesive gaps and a shaped plate-folding portion improve heat dissipation while limiting deformation in foldable displays.

Nickel oxide nanoparticles and a zinc oxide transport layer improve charge injection, luminance, efficiency, and lifespan in quantum dot emitters.

Segmented MIM capacitor regions with different voltage ratings support low- and high-voltage CMOS decoupling without series routing overhead.

Different microlens heights for image and phase detection pixels improve separation ratio, autofocus accuracy, and sensor sensitivity.

A carbon-nanotube resin anti-static layer dissipates static charge while preserving capacitance changes needed for accurate touch sensing.

Inclined facing edges between tiled micro LED modules reduce visible boundary lines while improving handling, mounting, and yield.

Inclined reflective walls and full-surface wavelength conversion raise μLED light output while reducing processing damage and semiconductor waste.

A universal redundant control gate driver and switch network replace failed word-line drivers to keep non-volatile memory operating.

Particle-beam lifetime control cuts reverse recovery loss while tuned contact-hole Ti silicide helps protect threshold voltage and gate dielectric reliability.

An inverted T-shaped bottom electrode concentrates the electric field to speed filament formation and improve RRAM programming.

An etch-stop landing stack and spacer isolation prevent punch-through and word-line shorts during 3D NAND staircase contact formation.

A grooved shielding layer blocks light from the glue area and constrains support-layer deformation, improving sensor accuracy and package reliability.

A nested red-green LED package equalizes DEP behavior across RGB chips, improving simultaneous micro-LED assembly speed, selectivity, and pixel scaling.

Wide insulated slot regions route contacts to source tiers in vertical memory stacks, raising density while simplifying contact formation.

By moving the driver IC behind the light-emitting surface, this micro LED panel layout cuts bezel size and avoids complex substrate processes.

A positive TCO bias on NAND dummy select transistors offsets temperature-driven threshold shifts and reduces program disturb.

A stacked micro-LED chip combines RGB sub-units with reinforced electrodes and passivation to simplify transfer while preserving brightness.

A protective cap controls channel pillar height during etching to isolate conductive pillars from the top word line and prevent leakage.

Independent conductive regions are formed in one lithography step to simplify 3D silicon capacitor fabrication and reduce alignment burden.

Software-based EP signal processing matches cardiac patterns while preserving low-amplitude signals and reducing ablation noise.

Plasma-tuned inhibition modulates tungsten nucleation in high-aspect-ratio vias and wordlines to avoid seams, voids, and resistance rise.

A vertical transfer gate and insulation wall help backside image sensor pixels move photogenerated charges with less trapping and fewer potential minima.

Stitch-bonded wire connections and split pad regions cut stray light, crosstalk, and size growth in compact photodetectors.

Using SiOCN sidewall spacers cuts parasitic capacitance in RF switches, improving isolation and insertion loss while avoiding etch damage.

A series resistor and grounded capacitor let a Ge photodetector keep L-band sensitivity while avoiding breakdown at high optical input power.

Different aperture ratios across pixel regions redirect incident light away from isolation structures to improve sensor uniformity and image quality.

A sloped metal light-blocking pattern guides spin coating to improve thickness uniformity in optical black, pad, and connection regions.

Segmented photo- and thermo-curable adhesives block stray light at the image sensor package edge while maintaining bonding strength and sensing accuracy.

Stacked and folded ferroelectric capacitors share a common node to cut bit-cell area, lower write power, and improve memory endurance.

Overlapping movable frames press the substrate during fluid self-assembly, preventing buoyancy damage while improving microLED transfer accuracy.

A wider upper gate cut keeps through vias from overlapping stacked gate electrodes, preventing shorts while preserving transistor scaling.

Segmented pixel groups with refractive light-guiding structures improve color capture, sensitivity, and dynamic range in image sensors.

Sidewall protective structures block etching solution from peripheral metal wires, reducing shorts, opens, and yield loss in AMOLED array substrates.

An electro-optic modulator between the color filter and sensor shifts focal length and refractive index to cut TOF interference and speed PDAF.

Separating driving circuits and power lines onto two substrates prevents TFT-related voltage drop and abnormal LED display.

Separated openings in stacked insulating layers maintain metal-layer connection while reducing peeling, impedance, noise, and yield loss.

Uneven electrode and dielectric surfaces raise DRAM capacitor area and capacitance without the toppling risk of elongated columnar structures.

Cavities between ReRAM electrodes cut parasitic capacitance, stabilize switching fields, and reduce current spikes and power use.

A dual silicon oxynitride tunneling film raises barrier height and preserves charge trapping to improve nonvolatile memory data retention.

Fast ToF gating in a compact global shutter pixel cuts sensor size and power while preserving depth measurement accuracy for mobile vision.

Post-baked photoresist flows into the channel to protect the TFT back channel during oxide semiconductor etching while avoiding an extra mask.

Distinct HKMG high- and low-voltage regions use recessed substrate geometry and thicker dielectrics to cut leakage, contact resistance, and junction risk.

Sacrificial studs keep molding compound off the transmitter and receiver, creating isolated cavities for simpler calibration and smaller sensor packages.