PG-Aligned Cell Layout for Semiconductor Routability and Continuity

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Solution Overview

Problem

In semiconductor device layout generation, area utilization by standard functional cells exceeding 80% leads to diminished routability, noise profile deterioration, and timing failures due to insufficient space for signal routing.

Innovation Solution

The implementation of a power-grid layer with conductive metallization layers and monostate cells, such as tap cells and decoupling capacitor cells, which are arranged in a repeating relationship to overlap with metallization segments, ensuring electrical continuity and uniform planarity, thereby optimizing area utilization and routability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If area utilization by standard functional cells exceeds 80%, then area utilization is improved, but routability is significantly diminished

Engineering Contradiction:

Improvearea utilizationVSAvoidroutability

Core Design Contradiction:

Area of stationary objectVSEase of operation

Solution Approach 1:

The layout is segmented into functional cell regions and power-grid regions, with monostate cells strategically positioned at power-grid intersections. This segmentation allows high area utilization in functional regions while maintaining dedicated space for power distribution without compromising routability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical layering dimension by placing monostate cells at the intersection of power-grid rows and columns, creating a three-dimensional arrangement that optimizes both area utilization and power distribution effectiveness without interfering with horizontal signal routing.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If area utilization by standard functional cells exceeds 80%, then area utilization is improved, but noise profile deteriorates significantly

Engineering Contradiction:

Improvearea utilizationVSAvoidnoise profile

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

Monostate cells serve as intermediary elements between power-grid intersections and functional cells. These intermediary cells provide localized power regulation and noise filtering, reducing the noise impact on functional cells while maintaining high area utilization.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies local quality by positioning monostate cells specifically at power-grid intersections where noise is most critical, rather than uniformly distributing them. This targeted approach addresses noise problems in high-density regions while preserving area utilization efficiency.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If area utilization by standard functional cells exceeds 80%, then area utilization is improved, but timing failures occur

Engineering Contradiction:

Improvearea utilizationVSAvoidtiming failures

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

Monostate cells are placed in advance at power-grid intersections to establish stable power distribution networks before functional cells are positioned. This preliminary action ensures that power and ground connections are already optimized, preventing timing failures even at high area utilization.

Inventive Principle:

Principle #10Preliminary action

4Reliability

If monostate cells are arranged to overlap with metallization segments, then electrical continuity is maintained, but device complexity increases

Engineering Contradiction:

Improveelectrical continuityVSAvoidlayout complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Monostate cells perform multiple functions: they maintain electrical continuity with power-grid metallization, provide local power regulation, and serve as noise filtering elements. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12112117B2Method of manufacturing a semiconductor device including PG-aligned cells

Publication Date: 2024.10.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of manufacturing a semiconductor device includes forming a set of cells; forming a PG layer, including forming a first metallization layer including forming first conductor portions and second conductor portions, corresponding ones of the first conductor portions being arranged in first pairs; corresponding ones of the second conductor portions being arranged in second pairs; the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and forming a second metallization layer over the first metallization layer, the second metallization layer including forming third conductor portions and fourth conductor portions, the cells being arranged in a repeating relationship that each cell overlaps, an intersection of a corresponding one of the first or second pairs with at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.