Stacked Folded Ferroelectric Bit-Cell Layout for Higher Memory Density
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Solution Overview
Problem
Conventional non-volatile memories, such as MRAM and flash memories, are not suitable for low-power and compact computing devices due to high write energy, low density, and high power consumption, while existing capacitor designs occupy large areas, making them challenging for miniaturization.
Innovation Solution
The use of stacked and folded capacitor configurations in memory bit-cells, where capacitors are vertically stacked and folded along a common node, reducing the vertical height of the circuit and maximizing transistor footprint, combined with endurance mechanisms like wear leveling and refresh schemes to mitigate charge disturbance and enhance memory endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional non-volatile memories (MRAM, flash) are used, then non-volatility is achieved, but write energy consumption is high and power consumption is high
Solution Approach 1:
The patent replaces conventional non-volatile memory mechanisms (magnetic storage in MRAM, charge trapping in flash) with a ferroelectric-based system that uses electric field-induced polarization switching. This substitution enables non-volatile data storage with lower energy consumption by utilizing the high coercive field and hysteresis characteristics of ferroelectric materials, which require less energy for state transitions compared to magnetic or charge-trapping mechanisms.
Solution Approach 2:
The patent changes the fundamental storage parameter from magnetic moment (MRAM) or trapped charge (flash) to ferroelectric polarization state. By utilizing the bistable polarization states (+Pr and -Pr) of ferroelectric materials, the system achieves non-volatile storage with lower write energy, as the polarization switching occurs at lower energy thresholds compared to magnetic domain switching or charge injection/extraction processes.
2Stability of the object's composition
If conventional non-volatile memories are used, then non-volatility is achieved, but density is low
Solution Approach 1:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor configurations. By stacking multiple ferroelectric capacitors vertically and sharing common electrodes, the design achieves higher storage density within the same footprint area. This vertical stacking approach allows multiple storage nodes to occupy the same lateral space, effectively utilizing the third dimension to increase density.
Solution Approach 2:
The patent merges multiple capacitor structures by sharing common electrodes. Specifically, the bottom electrode of one capacitor serves as the top electrode of the capacitor below it, and vice versa. This merging approach reduces the total number of electrodes required and increases storage density by allowing capacitors to be tightly packed in a stacked configuration without requiring separate electrode structures for each capacitor.
3Reliability
If multiple capacitors are used in memory bit-cells, then memory functionality is improved, but area occupancy increases
Solution Approach 1:
The patent resolves the area occupancy issue by stacking capacitors in the vertical dimension rather than placing them side-by-side in the lateral plane. Multiple capacitors are arranged in tiers with shared electrodes, allowing the memory bit-cell to maintain its functionality while occupying significantly less lateral area. The vertical stacking transforms the area problem into a height consideration, enabling higher density integration.
Solution Approach 2:
The patent implements a nested capacitor structure where capacitors are arranged in tiers with inner capacitors sharing electrodes with outer capacitors. The bottom electrode of an upper capacitor is nested within the structure of the lower capacitor, and common electrodes serve multiple capacitors simultaneously. This nesting approach maximizes space utilization and reduces the overall area required for multi-capacitor memory bit-cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area occupancy of capacitors, lowers power consumption, and improves memory endurance by minimizing charge disturbance and extending the lifespan of non-volatile memory cells, making them suitable for low-power and compact devices.
Implementation Method 1
The memory comprises a ferroelectric capacitor. The individual capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line.
Implementation Method 2
The plurality of capacitors is stacked and folded along a common node, reducing the vertical height of the circuit and maximizing transistor footprint
Implementation Method 3
The plurality of capacitors is stacked and folded along a common node, reducing the vertical height of the circuit and maximizing transistor footprint
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.