2D Power Clamp Cell Routing for Irregular Chip Blank Areas

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Solution Overview

Problem

The presence of deformed blank areas in chip layouts complicates the integration of ESD power clamp circuits, requiring redesign and additional planning burdens in chip design.

Innovation Solution

A two-dimensional puzzle power clamp cell with two-directional metal routing, allowing for flexible arrangement and connection of power clamp cells to fit any shape of the blank area, utilizing multiple metal layers for power and ground routing with insulation in between.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If ESD power clamp circuits are placed in deformed blank areas of chip layout, then the chip layout can be fully utilized, but the ESD power clamp circuits require redesign and additional planning

Engineering Contradiction:
Improveblank area utilizationVSAvoiddesign complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The power clamp circuit is divided into modular units with standardized power and ground routing interfaces. Each module can be independently designed and then assembled in various configurations to fit different blank area shapes, eliminating the need for redesign while maintaining full area utilization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power clamp modules are designed with universal power and ground routing that can connect in both horizontal and vertical directions. This multi-directional connectivity allows the same module design to be placed and connected in any arrangement, making the design universally adaptable to any blank area shape without requiring redesign

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of manufacture

If traditional power routing with single direction is used, then the routing is simple, but it cannot fit deformed blank area shapes

Engineering Contradiction:
Improverouting simplicityVSAvoidlayout adaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The power and ground routing is extended from single-direction (one-dimensional) to multi-directional (two-dimensional) connectivity. Power lines can route horizontally and vertically, and ground lines similarly have multi-directional paths, enabling the routing to adapt to deformed blank area shapes while maintaining manufacturing simplicity through standardized layer implementation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If power clamp cells are designed with fixed arrangement, then the design process is straightforward, but manual handling procedures are required for placement

Engineering Contradiction:
Improvedesign efficiencyVSAvoidplacement ease
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The power clamp module design incorporates dynamic adaptability through standardized multi-directional routing interfaces. The modules can be automatically arranged and connected by placement tools according to the blank area shape, transitioning from fixed static arrangements to flexible dynamic configurations that improve both design efficiency and placement ease

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4439668A1Two-dimensional power clamp cell
Publication Date: 2024.10.02 MEDIATEK INC
  • EP4439668A1 patent drawingFigure 1~2
  • EP4439668A1 patent drawingFigure 3~4
  • EP4439668A1 patent drawingFigure 5~6

AI summary

The present invention provides a power clamp cell including a power clamping circuit, a power routing and a global routing is disclosed. The power routing has at least a first vertical metal line and a first horizontal metal line, and the power routing is implemented by using a first metal layer in semiconductor process. The ground routing has at least a second vertical metal line and a second horizontal metal line, and the ground routing is implemented by using a second metal layer in the semiconductor process.