ReRAM Cavity Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Resistive memory devices experience large variations in resistive switching characteristics and increased parasitic capacitance with miniaturization, leading to performance degradation and power consumption issues due to current fluctuations and unwanted current spikes.
Innovation Solution
The design incorporates a resistive memory device with dielectric pillars, bottom electrodes, and a switching layer, featuring cavities between the pillars to reduce parasitic capacitance and stabilize electric fields, thereby improving performance and reducing power consumption by confining conductive paths and minimizing stochasticity in resistance switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistive memory devices are miniaturized to improve integration density, then device scaling is achieved, but parasitic capacitance and resistance of interconnection schemes increase, degrading chip performance
Solution Approach 1:
The patent extracts and removes the dielectric material between adjacent bottom electrodes, creating cavities that eliminate parasitic capacitance between neighboring electrodes. This directly addresses the harmful parasitic effects that increase with miniaturization while maintaining high integration density.
Solution Approach 2:
The patent introduces a porous or cavity-based structure between dielectric pillars, replacing solid dielectric material with void spaces. This porous configuration reduces parasitic capacitance between adjacent conductive elements while allowing the device to maintain compact dimensions for high integration density.
2Productivity
If device dimensions are reduced to increase integration density, then scaling is achieved, but current fluctuations increase causing performance degradation
Solution Approach 1:
By removing dielectric material between bottom electrodes to form cavities, the patent eliminates unwanted electrical coupling that causes current fluctuations. This extraction of harmful dielectric material stabilizes current flow while allowing continued device scaling for high integration density.
Solution Approach 2:
The patent applies different dielectric properties to different regions: cavities (void spaces) are created between bottom electrodes to reduce parasitic effects and stabilize current, while dielectric material is retained in other regions for insulation. This localized quality variation stabilizes current fluctuations while maintaining scaling capability.
3Object-affected harmful factors
If dielectric material is present between interconnect structures, then insulation is provided, but unwanted current spikes occur due to charging and discharging of parasitic capacitance
Solution Approach 1:
The patent extracts dielectric material from the spaces between bottom electrodes, creating cavities that eliminate parasitic capacitance. This removal prevents the charging and discharging effects that generate unwanted current spikes during resistance state switching, while insulation is maintained through alternative means.
Solution Approach 2:
The patent implements local quality variation by creating cavity regions between bottom electrodes where dielectric material is absent to prevent current spikes, while maintaining insulation properties through the cavity structure and surrounding dielectric layers. This localized approach eliminates harmful current spikes while preserving necessary insulation.
Data Source
AI summary
The disclosed subject matter relates generally to resistive memory devices and methods of forming the same. More particularly, the present disclosure relates to two terminal and three terminal resistive random-access (ReRAM) memory devices with a cavity arranged between electrodes.