Crown Capacitor Fabrication Using Differential Etching for Higher Capacitance
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Solution Overview
Problem
The capacitance of memory cell capacitors in semiconductor devices is critical for supporting the multifunctionality of electrical devices, and existing methods fail to adequately increase capacitance to ensure proper operation.
Innovation Solution
A method for fabricating a crown capacitor involves forming a stacking structure with alternating sacrificial layers, performing an etching process at different rates to create a wavy electrode layer, and subsequently removing the sacrificial layers to form a dielectric and second electrode layer, resulting in a structure with high capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor structures are used, then the manufacturing process is simple, but the capacitance is insufficient to support multifunctional electrical devices
Solution Approach 1:
The patent applies curvature by forming a wavy structure in the electrode layer through selective etching of sacrificial layers at different rates. This creates a crown-shaped capacitor with increased surface area and capacitance, directly addressing the insufficient capacitance issue while maintaining a manageable structural complexity through a systematic fabrication process
Solution Approach 2:
The patent transitions from a planar capacitor structure to a three-dimensional crown structure by forming alternating sacrificial layers and selectively removing portions at different depths. This dimensional change increases the effective capacitance volume without proportionally increasing manufacturing complexity, as the process follows a repeatable layer-by-layer pattern
2Reliability
If the capacitance is increased to support multifunctionality, then device operation is ensured, but the manufacturing process becomes more complex
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming alternating sacrificial layers with different etch rates, performing selective etching to create the wavy structure, removing sacrificial layers, and forming electrode and dielectric layers. This segmentation makes the complex capacitor fabrication manageable by breaking it into systematic, repeatable steps that ensure reliable device operation
Solution Approach 2:
The patent performs preliminary actions by first forming the alternating sacrificial layers with different compositions and etch rates before creating the final capacitor structure. This preliminary structuring enables subsequent selective etching to efficiently produce the desired wavy morphology, ensuring reliable capacitance enhancement while organizing the fabrication process into logical sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively increases the capacitance of memory cell capacitors, ensuring optimal operation of electrical devices by forming a crown capacitor with a wavy structure that enhances capacitance.
Implementation Method 1
performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate
Implementation Method 2
an annealing process is performed to the first and second sacrificial layers before performing the etching process. The annealing process is performed at a temperature ranging from about 600° C. to about 1000° C.
Implementation Method 3
forming a dielectric layer and a second electrode layer over the first electrode layer
Data Source
AI summary
A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.