Uneven-Junction ESD Diode Layout for High Current in Small Area

The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by forming impurity regions that extend in the depth direction of the semiconductor substrate. The first and second impurity regions are formed to have different depths, creating a vertical junction that increases the effective junction area without increasing the surface footprint, thereby improving current drivability while maintaining small device area.

The patent embeds one impurity region within another by forming the second impurity region inside the first impurity region. This nested configuration allows both impurity regions to contribute to current handling capability while occupying minimal surface area, effectively increasing the functional area for current flow without proportionally increasing the overall device area.

The patent uses vertical extension of impurity regions to increase the effective junction area in the depth direction, which compensates for the reduction in metal line quantity. The vertical junction structure provides multiple current pathways through the substrate depth, maintaining current drivability even with fewer metal interconnects.

The patent changes the depth parameter of impurity regions by forming the first impurity region at a first depth and the second impurity region at a second depth different from the first depth. This parameter variation creates a vertical junction that enhances current handling capability without requiring additional metal lines, thus improving integration density while maintaining reliability.