Gate Cut Layout for Isolating Stacked Gate Electrodes
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Solution Overview
Problem
Current semiconductor devices face challenges in preventing shorts between upper and bottom gate electrodes due to overlapping through vias, which affects the scalability and performance of multi-bridge channel field effect transistors.
Innovation Solution
The semiconductor device design features a gate cut structure where the width of the portion isolating the upper gate electrodes is greater than that isolating the bottom gate electrodes, allowing through vias to be positioned non-overlappingly with the upper gate electrodes, thereby preventing shorts and enhancing device scalability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If through vias are positioned directly under upper gate electrodes for simplified manufacturing, then manufacturing precision is improved, but short circuits occur between upper gate electrodes and through vias
Solution Approach 1:
The patent introduces a width dimension difference between the first gate cut (isolating bottom gate electrodes) and the second gate cut (isolating upper gate electrodes). The second gate cut has a greater width in the second horizontal direction, creating a wider isolation region that prevents through vias from overlapping with upper gate electrodes while maintaining manufacturing feasibility.
Solution Approach 2:
The patent employs asymmetric gate cut widths where the isolation structure for upper gate electrodes (second gate cut) is deliberately made wider than the isolation structure for bottom gate electrodes (first gate cut). This asymmetric design creates sufficient spacing to prevent short circuits while maintaining manufacturing simplicity.
2Reliability
If gate cut width is increased to prevent shorts, then electrical isolation reliability is improved, but device area increases
Solution Approach 1:
The patent applies different gate cut widths at different locations: the first gate cut (for bottom gate electrode isolation) has a standard width, while the second gate cut (for upper gate electrode isolation) has a greater width. This localized quality enhancement ensures reliable isolation only where needed (under upper gate electrodes) without unnecessarily increasing the overall device area.
Data Source
AI summary
In some embodiments, a semiconductor device includes a first active pattern extended in a first horizontal direction on a substrate, a second active pattern extended in the first horizontal direction on the substrate, a first bottom gate electrode extended in a second horizontal direction on the first active pattern, a first upper gate electrode extended in the second horizontal direction on the first bottom gate electrode, a second bottom gate electrode extended in the second horizontal direction on the second active pattern, a second upper gate electrode extended in the second horizontal direction on the second bottom gate electrode, and a first gate cut comprising a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode. A width of the second portion exceeds a width of the first portion.