Solid-State Imaging Element PAD Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In downsized semiconductor devices, the arrangement of PAD electrodes reduces circuit area, increases wiring distance, and generates parasitic capacitance, especially when formed in large semiconductor elements.
Innovation Solution
A solid-state imaging element configuration where a first semiconductor element with an imaging element is paired with a smaller second semiconductor element having a signal processing circuit, with the second element's circumference embedded with an embedded member and the PAD electrode formed within this member, allowing for improved area efficiency and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a PAD electrode is arranged in a wiring layer of a downsized semiconductor device, then the device can be miniaturized, but the arrangement area of the circuit is reduced
Solution Approach 1:
The PAD electrode is moved from the two-dimensional wiring layer plane to a three-dimensional structure by embedding it in a protruding embedded member that extends from the semiconductor element. This vertical dimensionality change allows the PAD electrode to occupy space above the element rather than competing for planar wiring area, thus maintaining circuit arrangement space while enabling miniaturization.
Solution Approach 2:
The PAD electrode is nested within the embedded member structure, which protrudes from the semiconductor element. This nesting arrangement allows the PAD electrode to be contained within a dedicated structural element rather than being placed in the wiring layer, freeing up circuit arrangement area while maintaining the electrode's functionality.
2Area of stationary object
If a PAD electrode is formed in a large semiconductor element, then the device can accommodate all components, but the wiring distance from a small semiconductor element to the PAD electrode becomes longer
Solution Approach 1:
The embedded member acts as an intermediary structure that physically bridges the gap between the small semiconductor element and the PAD electrode. By providing this intermediate platform that protrudes from the element, the wiring distance is reduced compared to placing the PAD electrode far away on the element surface, while the electrode remains accessible for external connections.
3Area of stationary object
If a PAD electrode is formed in a large semiconductor element, then all components can be accommodated, but the parasitic capacitance generated in the wiring increases
Solution Approach 1:
The PAD electrode is extracted from the main semiconductor element body and placed in a separate embedded member structure. This extraction reduces the parasitic capacitance by separating the high-capacitance PAD electrode from the element's internal wiring structure, thereby reducing the harmful capacitive effects while maintaining the element's functional area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances area efficiency for PAD electrode arrangement, reduces wiring damage during solder connections, and minimizes parasitic capacitance by embedding the PAD electrode in the embedded member, using materials with lower dielectric constants.
Implementation Method 1
an imaging element for photoelectrically converting incident light
Data Source
AI summary
The present disclosure relates to a solid-state imaging element, an imaging apparatus, and an electronic device that can reduce the effects caused by a PAD electrode being formed. When laminating a Logic substrate smaller than an image sensor, a through hole is formed in the image sensor in such a manner as to form a PAD electrode in an embedded member embedded around the logic substrate. The present disclosure can be applied to an imaging apparatus.