Tunnel Dielectric Thickness Control in Embedded Flash Memory Cells
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Solution Overview
Problem
Embedded flash memory cells face performance issues due to non-uniform thickness of the tunnel dielectric layer, which results from lateral oxide encroachment during thermal oxidation steps, affecting the voltage threshold window and overall reliability.
Innovation Solution
A method is employed to form a tunnel dielectric layer with a relatively uniform thickness by performing a first charge trapping dielectric etching process to create an opening over the logic region and a second etching process to remove the dielectric structure over the select gate region, preventing lateral oxide encroachment and maintaining the charge trapping dielectric structure over the select gate region during thermal gate dielectric formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform charge trapping dielectric structure is formed over the entire substrate including select gate regions, then the manufacturing process is simplified, but lateral oxide encroachment during thermal oxidation causes non-uniform tunnel dielectric layer thickness affecting memory performance
Solution Approach 1:
The substrate is divided into memory regions and select gate regions. The charge trapping dielectric structure is selectively formed only in memory regions while being removed from select gate regions, allowing different processing paths for different functional areas and preventing oxide encroachment in select gate regions
Solution Approach 2:
Different regions of the substrate are given different dielectric structures tailored to their specific functions. Memory regions receive the full charge trapping dielectric structure (tunnel dielectric layer, charge trapping layer, blocking dielectric layer) while select gate regions receive only a thin gate dielectric layer, optimizing each region for its intended purpose
2Manufacturing precision
If the charge trapping dielectric structure is removed over the select gate region, then lateral oxide encroachment is prevented and tunnel dielectric layer thickness uniformity is improved, but the manufacturing process complexity increases
Solution Approach 1:
The charge trapping dielectric structure is removed over select gate regions before the thermal oxidation step that forms the tunnel dielectric layer. This preliminary removal prevents oxide encroachment from occurring in the first place, eliminating the need for complex compensation techniques during or after tunnel dielectric layer formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance and reliability of embedded flash memory cells by maintaining a consistent tunnel dielectric layer thickness, reducing variations in threshold voltage and enhancing operational stability.
Implementation Method 1
lateral oxide encroachment during thermal oxidation steps
Implementation Method 2
charge trapping dielectric structure having a tunnel dielectric layer
Data Source
AI summary
Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.