Stacked Folded Planar Capacitors for Memory Data Retention
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Solution Overview
Problem
Traditional non-volatile memories, such as ferroelectric memories, suffer from charge degradation and disturbance due to the routing configuration of plate-lines relative to bit-lines and word-lines, leading to polarization decay and leakage, which affects data retention and reliability.
Innovation Solution
The implementation of a stacked and folded capacitor configuration with word-line boosting and refresh mechanisms, including wear leveling schemes and error correction, to mitigate charge disturbance and enhance memory endurance, while also optimizing capacitor placement to reduce parasitic capacitance and improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional non-volatile memories use conventional capacitor routing configurations, then the memory structure is simpler, but charge degradation and disturbance occur due to parasitic capacitance from plate-line routing
Solution Approach 1:
The patent transitions from planar capacitor routing to three-dimensional stacked capacitor configuration. Multiple capacitors are stacked vertically with shared bottom electrodes, moving the solution from two-dimensional layout to three-dimensional structure. This dimensional change reduces parasitic capacitance effects while maintaining data retention reliability.
Solution Approach 2:
The patent divides the memory structure into segmented capacitor units with individual top electrodes and shared bottom electrodes. Each capacitor in the stack is independently configured with plate-lines running perpendicular to bit-lines, segmenting the charge storage function across multiple stacked elements rather than using a single large capacitor.
2Reliability
If multiple capacitors are used in memory circuits, then data retention and reliability improve, but the area occupied by capacitors increases
Solution Approach 1:
The patent utilizes vertical stacking to accommodate multiple capacitors in the z-dimension rather than spreading them out in the x-y plane. By stacking capacitors vertically with shared bottom electrodes and perpendicular plate-line routing, the solution fits multiple high-capacitance elements into a compact footprint, reducing the overall area while maintaining reliability.
Solution Approach 2:
The patent merges multiple capacitor bottom electrodes into a shared common electrode structure. Instead of providing separate bottom electrodes for each capacitor, the design combines them into a single shared electrode that serves multiple stacked capacitors, reducing redundant material and minimizing the total area occupied by the capacitor array.
3Reliability
If plate-lines are routed parallel to bit-lines in traditional configurations, then the routing is simpler, but charge disturbance and polarization decay increase
Solution Approach 1:
The patent introduces asymmetric routing where plate-lines run perpendicular to bit-lines rather than parallel, creating an orthogonal configuration. This asymmetric arrangement minimizes the overlap and coupling between plate-lines and bit-lines, reducing parasitic capacitance and charge disturbance while maintaining routing manageability through systematic perpendicular alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces charge disturbance, enhances memory endurance, and improves data retention by minimizing the impact of parasitic capacitance and optimizing capacitor placement, leading to more reliable and efficient non-volatile memory operations.
Implementation Method 1
a first terminal of the plurality of ferroelectric capacitors is coupled to a storage node and a second terminal of the plurality of ferroelectric capacitors is coupled to a plate line
Implementation Method 2
optimizing capacitor placement to reduce parasitic capacitance and improve data retention
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.