3D NAND Staircase Contact Structure With Etch-Stop Isolation
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Solution Overview
Problem
In 3D NAND flash memory devices, the etching process for forming contact holes can cause punch-through issues, leading to short circuits between gate layers, and the use of thicker top sacrificial layers can result in leakage or shorts between word lines due to residue replacement during the gate layer formation process.
Innovation Solution
A semiconductor device with a landing stack and spacer isolation structure is introduced, where the landing stack includes an etch stop layer selective to the contact isolation layer, and a spacer isolation structure is used to prevent punch-through during contact hole etching, while the spacer isolation structure is formed in a recessed space of the etch stop layer to isolate the contact structure from the etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the etching process is used to form contact holes, then contact holes can be formed to connect driving circuitry to gate layers, but punch-through issues occur leading to short circuits between gate layers
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the contact isolation layer and the gate layers. This etch stop layer acts as a mediator that prevents the etching process from punching through to adjacent gate layers, thereby eliminating short circuits while still allowing contact holes to be formed to reach the intended gate layer.
Solution Approach 2:
The contact hole formation process is segmented into multiple stages with the etch stop layer providing a distinct intermediate layer. This segmentation allows the etching process to stop at a controlled depth, preventing penetration through the entire stack and avoiding damage to underlying structures.
2Reliability
If thicker top sacrificial layers are used, then leakage or shorts between word lines can be prevented, but residue replacement during gate layer formation causes manufacturing issues
Solution Approach 1:
The etch stop layer is formed with specific material composition and thickness parameters that enable it to provide adequate isolation (preventing leakage) while being selectively removable or replaceable during subsequent processing, thus avoiding the residue issues associated with thicker sacrificial layers.
Solution Approach 2:
The etch stop layer serves as a temporary structure that performs its isolation function during critical processing steps, then can be selectively removed or replaced without affecting the final device performance, similar to disposable sacrificial layers but with improved controllability.
3Reliability
If the landing stack with etch stop layer is introduced, then punch-through during contact hole etching is prevented, but device structure becomes more complex
Solution Approach 1:
The etch stop layer is integrated into the existing stack structure and serves multiple functions: preventing punch-through during etching, providing a planarization surface, and acting as a barrier layer. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the profile requirements of sidewalls in the staircase region, improves the process window for forming stair steps, and prevents leakage or shorts between word lines by using a thicker etch stop layer and spacer isolation structure, enhancing the reliability of contact hole etching.
Implementation Method 1
the landing stack includes an upper layer that is etch selective to a contact isolation layer that covers the staircase region
Implementation Method 2
the spacer isolation structure isolates the upper layer from the first contact structure
Data Source
AI summary
Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. Further, the semiconductor device includes a landing stack formed on the stair steps in the staircase region. The landing stack includes an upper layer that is etch selective to a contact isolation layer that covers the staircase region. Then, the semiconductor device includes a first contact structure on a first stair step of the stair steps. The first contact structure extends through a first contact hole in the contact isolation layer and the landing stack. The first contact structure is connected with a first gate layer (e.g., a top gate layer) of the first stair step.