Vertical Memory Stack Slot Structure for Simpler Tier Contacts
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing memory density and reducing fabrication complexity while maintaining performance, particularly in vertical memory array architectures where electrical connections and contact structures are intricate and costly to implement.
Innovation Solution
The design incorporates a stack structure with alternating insulative and conductive tiers, divided into blocks separated by slot structures, featuring stadium structures with opposing staircase structures and central regions, which allow for efficient electrical access and reduced complexity in contact formation by positioning conductive contact structures within wide slot regions filled with insulative material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical memory array architecture is used to increase memory density, then integration density is improved, but electrical connection complexity increases
Solution Approach 1:
The patent divides the electrical connection path into discrete segments using staircase contact holes at different vertical levels. Each contact hole connects to a specific tier of conductive structures, creating modular connection points that simplify the overall connection architecture while maintaining vertical integration density.
Solution Approach 2:
The patent transitions from planar (2D) routing to three-dimensional (3D) connection architecture by using vertically stacked contact holes at different heights. This dimensional change allows electrical connections to access conductive structures at multiple vertical levels without increasing lateral routing complexity.
2Reliability
If staircase structures are formed to provide electrical access to conductive material, then electrical connectivity is improved, but fabrication complexity increases
Solution Approach 1:
The patent combines the formation of multiple contact holes at different vertical levels into a single integrated fabrication process sequence. By forming contact holes for multiple tiers simultaneously or in close succession using the same lithography and etching tools, the patent reduces the cumulative fabrication complexity that would otherwise result from separate processing steps for each contact level.
3Area of moving object
If feature dimensions are reduced to increase integration, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediary contact hole structures that serve as mediators between the reduced-dimension conductive features and the larger-dimension routing structures. These intermediate contact holes provide a buffer zone that is easier to manufacture with standard precision, while still enabling connection to the high-density vertical features through controlled etching and alignment processes.
Data Source
AI summary
A microelectronic device includes a stack structure including tiers each including insulative material and conductive material vertically adjacent the insulative material. The stack structure divided into at least two blocks separated from one another. The microelectronic device further includes at least one slot structure horizontally interposed between the at least two blocks of the stack structure. The at least one slot structure including additional insulative material and at least one contact structure extending through the additional insulative material to source tier underlying the stack structure.