Shared-Pixel CMOS Imager Layout to Limit Floating Diffusion Capacitance
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Solution Overview
Problem
CMOS image sensors face challenges in reducing pixel size while maintaining sensitivity and full well capacity, as well as preventing increases in junction and wiring capacitance, which can lead to decreased conversion gain and noise characteristics.
Innovation Solution
The design incorporates a solid-state imaging device with sharing pixels, where at least three photoelectric conversion elements share a floating diffusion and source follower element, arranged such that the floating diffusion is centered with photoelectric conversion elements radially around it, and transfer elements connect the floating diffusion's lateral parts to the photoelectric conversion elements, optimizing spacing to minimize capacitance and prevent charge mixing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple pixels share one floating diffusion and source follower transistor, then pixel size is reduced, but junction capacitance and wiring capacitance increase
Solution Approach 1:
The patent divides the pixel array into multiple banks, where each bank contains a subset of pixels that share common readout circuitry. This segmentation allows for reduced pixel size within each bank while limiting the capacitance impact to only the pixels within that bank, rather than affecting the entire array.
Solution Approach 2:
The patent introduces a bank dimension in addition to the traditional row and column dimensions. Pixels are organized into banks along the column direction, creating a hierarchical structure where readout operations can be performed on a bank level, thereby reducing the effective wiring length and capacitance for each pixel group.
2Area of moving object
If multiple pixels share one floating diffusion and source follower transistor, then pixel size is reduced, but conversion gain decreases due to increased capacitance
Solution Approach 1:
By segmenting the pixel array into multiple banks with separate readout paths, the patent ensures that the capacitance load on each floating diffusion and source follower transistor is limited to only the pixels within its bank. This segmentation preserves conversion gain while still achieving pixel size reduction through sharing within each bank.
Solution Approach 2:
The patent changes the operational parameters by introducing bank-level readout timing control, where specific rows within specific banks are read out at different times. This parameter change allows for optimized capacitance management and conversion gain maintenance while enabling pixel sharing for size reduction.
3Area of moving object
If multiple pixels share one floating diffusion and source follower transistor, then pixel size is reduced, but noise characteristics deteriorate
Solution Approach 1:
The patent segments the pixel array into multiple banks with independent readout paths, which isolates noise within each bank. This segmentation prevents noise from accumulating across the entire array, thereby maintaining noise characteristics while achieving pixel size reduction through sharing within each bank.
Solution Approach 2:
The patent extracts the readout circuitry (floating diffusion and source follower transistor) from being completely shared across all pixels in a column, and instead allocates dedicated readout circuitry to each bank. This extraction reduces the noise impact on individual pixels while still allowing for size reduction through partial sharing within banks.
4Device complexity
If multiple pixels share one floating diffusion and source follower transistor, then manufacturing complexity is reduced, but charge mixing between pixels may occur
Solution Approach 1:
The patent segments the pixel array into multiple banks with clear spatial and operational boundaries. This segmentation provides natural isolation between pixel groups, preventing charge mixing while still allowing for simplified manufacturing through shared circuitry within each bank. The bank structure creates implicit charge isolation regions.
Solution Approach 2:
The patent introduces bank-level control structures and timing mechanisms as intermediaries between individual pixels and the readout circuitry. These intermediary structures manage charge transfer and readout timing to prevent charge mixing between pixels while maintaining the simplified shared architecture within each bank.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces pixel size without compromising sensitivity or full well capacity, while preventing increases in capacitance and noise, thereby enhancing noise characteristics and preventing charge mixing between pixels.
Implementation Method 1
The first and second photodiodes PD0 and PD1 perform photoelectric conversion to generate charges
Data Source
AI summary
A source follower element is adjacent to a first lateral part of a floating diffusion in a first direction orthogonal to the first lateral part, a reset element is adjacent to a second lateral part of the floating diffusion in the first direction, and the floating diffusion and the source follower element are connected through a wiring. Some of the photoelectric conversion elements are adjacent to each other in a second direction and spaced away from each other with a first spacing therebetween that allows at least the source follower element and the reset element to be formed therein. Some of the photoelectric conversion elements are adjacent to each other in the first direction and spaced away from each other with a second spacing therebetween that is less than the first spacing.