3D Fan-Out Package Structure for High-Density Chip Stacking
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Solution Overview
Problem
Current system-level packaging technologies face challenges with large package area, low conformability, and low integration, failing to meet demands for ultra-high-density component packaging.
Innovation Solution
A three-dimensional fan-out integrated package structure is developed, comprising stacked semiconductor chips with rewiring layers, metal connection pillars, filler and encapsulating layers, and functional chips, reducing minimum line width/line spacing to 1.5 μm/1.5 μm, and incorporating a packaging method that includes forming rewiring layers and connecting functional chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional system-level packaging technology is used, then basic integration is achieved, but package area is large and integration density is low
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to three-dimensional stacked packaging by adding vertical dimension. Multiple semiconductor chips are stacked in the height direction with rewiring layers between them, enabling ultra-high-density integration while reducing package footprint area.
Solution Approach 2:
The patent implements nested structure where multiple semiconductor chips are stacked within a compact package volume. The chips are arranged in layers with rewiring layers nested between them, creating a space-efficient nested configuration that maximizes integration density.
2Quantity of substance
If more chips are integrated in limited space, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the packaging structure into standardized modular units consisting of semiconductor chips, rewiring layers, and encapsulating layers. Each layer serves a specific function and can be manufactured independently, reducing overall manufacturing complexity despite high integration density.
Solution Approach 2:
The rewiring layers serve multiple functions: electrical connection between stacked chips, signal routing, and structural support. This multi-functionality reduces the need for additional specialized components, simplifying the overall manufacturing process while maintaining high integration density.
3Area of stationary object
If chips are stacked vertically, then package area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements localized alignment features and precision structures at critical interfaces between stacked chips and rewiring layers. By concentrating precision requirements at specific locations rather than throughout the entire structure, manufacturing complexity is managed while achieving compact vertical stacking.
Data Source
AI summary
A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 μm/1.5 μm. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.