3D Fan-Out IC Package Structure With PCB Mechanical Support
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization, higher speed, greater bandwidth, lower power consumption, and latency, which require innovative packaging techniques for semiconductor dies.
Innovation Solution
The development of a standalone three-dimensional (3D) integrated fan-out (InFO) package and printed circuit board (PCB) structure, which involves forming a carrier substrate with a buffer layer, attaching integrated circuit dies, forming redistribution layers, and connecting the structure to a PCB for enhanced mechanical support and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor process node is reduced to sub-20 nm to increase integration density, then more components can be integrated into a given area, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked architecture, where multiple semiconductor dies are vertically stacked and interconnected through through-silicon vias (TSVs). This dimensional change allows continued increase in integration density without further reduction in lateral feature sizes, thereby avoiding the manufacturing precision challenges associated with sub-20 nm processes.
Solution Approach 2:
The patent implements a nested structure where multiple functional layers (semiconductor dies, interconnect layers, passivation layers) are stacked one inside another vertically. Each die contains complete functional circuits, and they are nested together through vertical interconnections, achieving high integration density without requiring extreme miniaturization of individual components.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components fit in a given area, but device complexity and manufacturing difficulty increase
Solution Approach 1:
By moving to three-dimensional stacking, the patent achieves high integration density through vertical arrangement rather than lateral miniaturization. This approach maintains simpler two-dimensional circuit patterns within each die layer while increasing overall capacity through the third dimension, thereby reducing device complexity compared to continued planar scaling.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate semiconductor dies, each containing a subset of the total functionality. These segmented dies are then stacked and interconnected, allowing each individual die to maintain manageable complexity while the overall system achieves high integration density through the combination of multiple segments.
3Ease of manufacture
If conventional packaging is used for miniaturized devices, then manufacturing is simpler, but mechanical strength and reliability are insufficient for secure installation
Solution Approach 1:
The patent employs a composite packaging structure combining multiple materials with complementary properties: semiconductor dies provide electrical functionality, ceramic or metal substrates provide mechanical strength and thermal management, encapsulant materials provide protection and insulation, and solder materials provide reliable electrical and mechanical connections. This composite approach achieves both ease of manufacture through standardized processes and superior mechanical strength for secure installation.
Solution Approach 2:
The patent implements a nested packaging architecture where semiconductor dies are nested on a substrate, which is then nested within an encapsulant, which is finally nested within a protective housing or connector assembly. Each nested layer provides specific functions (electrical, mechanical, protective) while maintaining ease of manufacture through sequential assembly processes.
Data Source
AI summary
An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.