3D Ferroelectric Memory Array Architecture for High Density
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Solution Overview
Problem
Conventional ferroelectric field-effect transistor (FeFET) memory arrays suffer from non-uniform series resistance and large feature sizes, limiting cell density and practicality due to their two-dimensional architecture.
Innovation Solution
A three-dimensional memory array architecture is implemented, where FeFETs are stacked horizontally and vertically with ferroelectric material separating the FET structures and gates, allowing for a high-density, low-power memory array with random access capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a two-dimensional memory array architecture is used, then the structure is simple and easy to manufacture, but the cell density is low and feature sizes are large
Solution Approach 1:
The patent transitions from a two-dimensional planar memory array to a three-dimensional vertical stack architecture. Multiple FeFET devices are stacked vertically to form memory cells, with bit lines extending in the x-direction and digit lines in the z-direction. This dimensional change increases cell density without compromising manufacturability, as the vertical stacking can be integrated with existing semiconductor fabrication processes.
2Device complexity
If source contacts and drain contacts are on the same side of the memory array, then the structure is simplified, but the series resistance is non-uniform across different FeFET positions
Solution Approach 1:
The patent positions source contacts and drain contacts on opposite ends of the memory array in the x-direction. Bit lines extend from one end to the other, allowing current to flow uniformly through all FeFET devices regardless of their vertical stack position. This opposite-side contact configuration ensures uniform series resistance across the array while maintaining structural simplicity.
3Device complexity
If conventional two-dimensional FeFET memory arrays are used, then the device structure is simple, but power consumption is high and cycling performance is limited
Solution Approach 1:
The vertical stack architecture enables more efficient current confinement and reduced leakage paths compared to planar devices. The stacked configuration improves cycling performance by reducing stress on individual device layers and enables lower power consumption through better control of the ferroelectric switching process in three dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D architecture achieves higher cell density, lower power consumption, and improved cycling performance compared to conventional memory arrays while maintaining random access capabilities.
Implementation Method 1
Each FeFET 110 may include a gate 118 separated from the FET structure by a ferroelectric material 120. The state of the FeFET 110 may be based on the polarization of the ferroelectric material 120 that may be switched in the presence of an external field.
Data Source
AI summary
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.