3D FeFET Memory Stack Using Mobility-Tuned Channel Layers
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits has increased complexity in processing and manufacturing, particularly for 3D memory devices, where existing technologies have not fully addressed the challenges of achieving efficient data storage and read operations with reduced layout area and improved power efficiency.
Innovation Solution
A 3D memory device is designed with ferroelectric field effect transistors (FeFET) using vertically stacked memory cells, featuring oxide semiconductor channel regions and ferroelectric material as gate dielectrics, allowing for different electron mobilities in channel layers to enable efficient data storage and read operations with reduced layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 3D memory device is introduced to replace planar memory device, then functional density is increased, but processing and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to three-dimensional (3D) stacked memory architecture. Multiple memory cell layers are vertically stacked above a common substrate, with word lines extending horizontally through each layer. This dimensional change increases storage capacity per unit area while the patent addresses the associated processing complexity through coordinated formation of vertical and horizontal conductive structures.
2Productivity
If 3D memory device is introduced to replace planar memory device, then functional density is increased, but manufacturing complexity increases
Solution Approach 1:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer containing memory cells formed between vertical bit line structures and horizontal word line structures. This segmentation allows for systematic fabrication through repeated deposition and patterning cycles, making the complex 3D structure manufacturable through modular processing steps.
Solution Approach 2:
The patent employs three-dimensional stacking of memory cell layers with vertical bit lines and horizontal word lines intersecting at right angles. This 3D architecture increases storage density while the patent manages manufacturing complexity by establishing clear fabrication sequences for forming vertical conductive structures, depositing dielectric layers, and patterning horizontal word lines across multiple layers.
3Area of stationary object
If conventional memory cells are used, then layout area is larger, but storage capacity per area is lower
Solution Approach 1:
The patent implements vertical stacking of multiple memory cell layers (e.g., five layers shown) above a common substrate area. Each layer contains memory cells formed by the intersection of vertical bit lines and horizontal word lines. This 3D arrangement dramatically increases storage capacity per unit footprint compared to conventional planar arrays, as the same substrate area supports multiple times the number of memory cells through vertical multiplication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for efficient data storage and read operations with reduced layout area and improved power efficiency, as only three memory cells with different on-currents are needed to store 3-bit data, enhancing the storage capacity and power efficiency of the 3D memory device.
Implementation Method 1
a gate dielectric layer including a ferroelectric material
Implementation Method 2
oxide semiconductor channel layers having different electron mobilities
Data Source
AI summary
A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.