Digital Storage TRIZ Cases
- FeFET Memory Gate Biasing for Faster Read-After-Write
An opposite-polarity non-zero gate bias cuts FeFET trap neutralization time, enabling accurate reads soon after writing.
- Subword Driver Layout With Shared Transistors for Tighter Memory Pitch
Shared transistors between adjacent subword drivers cut interconnection pitch and die area in dense memory array layouts.
- Vertical Resistive Memory Stack With Graphene and BN Layers
Graphene gate electrodes and BN insulation cut roughness and leakage, enabling thinner layers, higher mobility, and denser vertical memory stacks.
- Nanostructure SRAM Cell Stress Layout for Read Reliability
Different stress depths in access and pull-down nanostructure transistors raise pull-down current and reduce SRAM read failures.
- Dual-Free-Layer MRAM Writing Without Precise Pulse Width Control
A dual free-layer MRAM element uses VCMA and non-VCMA layers to simplify writing and avoid precise pulse width control.
- Doped Ferroelectric Memory Cells for Sub-5 nm Polarization Stability
A dopant concentration gradient helps thin ferroelectric layers crystallize below 5 nm, preserving polarization and enabling denser memory arrays.
- FeFET Synapse Pairing for Linear Neuromorphic Weight Response
Parallel FeFETs with different coercive voltages create discrete conductance states for more linear synaptic weights in neuromorphic processors.
- 3D Memory Conductive Spacer Structure for Lower Interface Traps
A conductive spacer with a different work function cuts interface traps and improves adhesion, extending 3D memory array endurance.
- FeRAM MFM Electrode Etch Layout for Undamaged Ferroelectric Storage
Selective electrode etching confines plasma-damaged ferroelectric regions outside the storage area, improving FeRAM reliability and lifespan.
- p-MTJ Free Layer Boron Extraction for Higher Magnetic Moment
Low-power plasma oxidation and annealing remove boron from the p-MTJ free layer, boosting magnetic moment, anisotropy, and thermal stability.
- FeFET NAND Memory Cell Layout for Read Margin and IR Drop
A shared-terminal FeFET and second transistor layout boosts cell current to improve read margin and speed under ferroelectric variability and IR drop.
- FeRAM Cell Structure for Non-Destructive Readout
A dual-select-transistor FeRAM cell separates write and read paths to prevent state destruction and remove write-back after reading.
- W-Si SOT Magnetic Tunnel Junction for Low-Resistance Switching
A W-Si spin-orbit active layer boosts SOT efficiency at low resistance while preserving perpendicular magnetic anisotropy after thermal treatment.
- Single-Layer Biaxial MRAM With Current-Only Magnetization Switching
Current-driven spin-orbit fields switch magnetization in a single biaxial ferromagnetic layer, cutting MRAM complexity and power use.
- Bismuth-Doped Ferroelectric Memory Cells for Thin-Film Scaling
Bismuth-doped hafnium oxide preserves ferroelectric behavior in thinner memory films, boosting remnant polarization and readout signal.