Digital Storage TRIZ Cases

An opposite-polarity non-zero gate bias cuts FeFET trap neutralization time, enabling accurate reads soon after writing.

Shared transistors between adjacent subword drivers cut interconnection pitch and die area in dense memory array layouts.

Graphene gate electrodes and BN insulation cut roughness and leakage, enabling thinner layers, higher mobility, and denser vertical memory stacks.

Different stress depths in access and pull-down nanostructure transistors raise pull-down current and reduce SRAM read failures.

A dual free-layer MRAM element uses VCMA and non-VCMA layers to simplify writing and avoid precise pulse width control.

A dopant concentration gradient helps thin ferroelectric layers crystallize below 5 nm, preserving polarization and enabling denser memory arrays.

Parallel FeFETs with different coercive voltages create discrete conductance states for more linear synaptic weights in neuromorphic processors.

A conductive spacer with a different work function cuts interface traps and improves adhesion, extending 3D memory array endurance.

Selective electrode etching confines plasma-damaged ferroelectric regions outside the storage area, improving FeRAM reliability and lifespan.

Low-power plasma oxidation and annealing remove boron from the p-MTJ free layer, boosting magnetic moment, anisotropy, and thermal stability.

A shared-terminal FeFET and second transistor layout boosts cell current to improve read margin and speed under ferroelectric variability and IR drop.

A dual-select-transistor FeRAM cell separates write and read paths to prevent state destruction and remove write-back after reading.

A W-Si spin-orbit active layer boosts SOT efficiency at low resistance while preserving perpendicular magnetic anisotropy after thermal treatment.

Current-driven spin-orbit fields switch magnetization in a single biaxial ferromagnetic layer, cutting MRAM complexity and power use.

Bismuth-doped hafnium oxide preserves ferroelectric behavior in thinner memory films, boosting remnant polarization and readout signal.

Heavy-metal and 3d transition-metal SHE alloys cut SOT-MRAM programming current and switching energy while improving data retention.

Vertically stacked FeFET cells use ferroelectric layers and different channel mobilities to store 3-bit data with less area and power.

A ferroelectric NCFET gate boosts on-current at lower gate voltage, cutting power use in MRAM and FeRAM memory structures.

Current-induced spin-orbit torque and Dzyaloshinskii-Moriya interaction enable selective MRAM switching without external magnetic fields.

Layered oxide memory cells increase storage density per area while simplifying stacking and avoiding high-voltage charge injection.

Recessed dielectric layers create 3D TFT channels that strengthen the electric field at lower gate voltage for faster writes and denser memory.

Placing the SRAM data backup unit in the BEOL enables faster restore, concurrent backup operations, and a smaller cell footprint.

Low-power plasma, natural oxidation, and annealing remove boron from the p-MTJ free layer to raise magnetic moment, PMA, and thermal stability.

Work function conductive spacers cut interface traps between word lines and memory films, improving 3D memory endurance and adhesion.

Recessed dielectric layers create 3D TFT channels that boost electric field strength, enabling faster memory writes at lower gate voltages.

A conformal sidewall dielectric and selective metal cap prevent electrode shorting in scaled ferroelectric capacitors for low-voltage, high-density memory.

A recessed spin-orbit torque wiring structure blocks impurity reattachment during ion beam cleaning, preserving magnetic characteristics and element life.

Series-connected MFM capacitors split input voltage to limit dielectric breakdown stress while sharing FeRAM fabrication to save chip area and cost.

Vertically stacked FeFET cells use channel layers with different electron mobilities to store 3-bit data in less area with lower read power.

Varying Fe concentration and layer thickness by cell height keeps MR, Hk, and coercive force uniform in stacked magnetic memory cells.

A vertical gated ferroelectric cell built in BEOL uses gate-all-around control and a current selector to raise memory density beyond CMOS limits.

An Fe-yX templating layer enables perpendicular Heusler free-layer growth while moving the SAF stack below the barrier for higher annealing tolerance.

An insulating spacer between closely spaced front gates enables precise contact formation and smaller Z2-FET memory cells without extra masks.

Openings that expose magnetic tunnel junction surfaces lengthen the current path, cut leakage current, and improve STT-MRAM state reliability.

A chiral PSM layer beside the MTJ free layer adds spin torque, cutting switching current without thicker stacks or lateral SOT lines.

Secondary access transistors isolate digit lines until both switches turn on, enabling selective DRAM cell access with lower power and less data dumping.

Alternating boron supply and adsorption layers limit MTJ interface diffusion during high-temperature processing and raise breakdown voltage.

A high-oxygen-affinity oxide layer suppresses oxygen interdiffusion in the MTJ free layer, stabilizing PMA and enabling sub-10 ns switching.

A stacked ferromagnetic and antiferromagnetic oscillator uses in-plane current to cut threshold current density while tuning terahertz precession.

A three-layer MTJ cap blocks diffusion and suppresses Ru hcp effects, preserving perpendicular anisotropy and TMR in MRAM.

A synthetic antiferromagnet enables magnetic tunneling junction switching without an external field, simplifying MRAM structure while keeping fast, stable operation.

A laminated spin conduction and spin generation stack lowers resistance while sustaining spin Hall and Rashba effects for magnetic memory switching.

A sidewall tunneling layer adds an electron path in MRAM magnetic tunnel junctions, lowering on-resistance without thinning the insulating layer.

Spin-orbit torque and Dzyaloshinskii-Moriya interaction enable selective MRAM switching without external magnetic fields.

Using oxide semiconductor access transistors cuts parasitic bitline capacitance and leakage, extending retention time and reducing memory power.

A top-pinned MRAM stack uses pre-annealed crystalline barrier layers to raise TMR while avoiding PMA loss and metal diffusion.

Varying oxide and ferroelectric layer thicknesses let one ferroelectric bit cell store multiple bits, increasing density while limiting chip area.

A rotating PSC layer and nonmagnetic insertion layer cut MRAM switching current while preserving free-layer stability and deterministic switching.

A ferroelectric gate stack uses controlled negative capacitance to cut subthreshold swing and improve switching speed and reliability in memory elements.

Latch and comparator pipelines hold the DQS line at fixed or prior values to prevent metastability and speed memory write initialization.

Non-volatile CES routing stores FPGA switch states locally, removing external memory to shrink device size and improve scalability.

Selective superconducting latches route current in either direction through a load, enabling precise memory-state control in cryogenic circuits.

Cross-coupled cascode level shifting stabilizes thin-oxide FET operation, avoiding metastability and damaging overvoltage in scaled nodes.

By storing write and read addresses inside the RAM block, this shift register removes separate control circuits to save area and power.

A two-level NVRS crossbar uses redundant switches and routing to bypass fixed ON and OFF defects while limiting area and power overhead.

Parallel state-machine lattices speed pattern matching while an error detection engine validates symbol response memory against bit corruption.

Alternating edge-triggered latch stages enable DDR channel selection with fewer address lines, shrinking CMOS image sensor decoding circuitry.

Selection logic bypasses storage stages so input data reaches output sooner, cutting clock-to-output lag while tolerating skew and jitter.

Algorithmic address and data generation refreshes Reed-Solomon memory to correct SEU errors with less ECC circuitry and better long-term reliability.

Row-wise power gating lets selected memory rows be grounded or tri-stated during writes, improving low-voltage write margin and speed.

Multiple selectable delay circuits tune data strobe and data paths to preserve memory capture margin at high speed and low voltage.

By holding the transmission line at a specified level after strobe output, this circuit discharges residual bus energy and prevents ringing.

Multiple configuration memory banks let an SoC programmable logic accelerator switch logic without runtime load penalties or wasted FPGA resources.

Parameter values are split across separate memories so a secure partial value can keep electronics operating when corruption affects the other memory.

A constant reference voltage with mode-based threshold adjustment preserves high-speed memory signal integrity while limiting POD power draw.

Multiple local storage units and shared address control let FPGA memory scale flexibly without excess logic use or wasted block memory.

A shared well region lets PMOS Yi and latch transistors keep write-time benefits without increasing sense amplifier area.

Counts and compares enabled pipe input and output signals, then initializes the latch path on mismatch to prevent abnormal semiconductor operation.

Variable strobe delay and reference-voltage feedback improve memory read training accuracy by reducing ISI in low-power, high-speed operation.

Selective current-path switching with MTJ elements blocks leakage in inverter outputs, cutting signal delay and power use in memory circuits.

Interleaved parity checking and tree-structured XOR logic speed soft error detection in memory circuitry while limiting disruption and reload power.

Using variable resistive magnetic elements and magnetic logic gating, this case shows how spin logic can retain states without repeated spin-to-charge conversion.

Direct pull-up and pull-down transition circuits bypass sequential NAND delays to speed latch edges and shorten memory access time.

Cross-stored single-bit repair arrays enable parallel bank access to correct resistive memory bit failures in real time with lower latency.

A mode-detecting signal generator holds trigger states beyond clock changes, enabling stable data output for write leveling and test modes.

An internal reference voltage tracks operating changes to filter memory-access noise, improve data comparison accuracy, and avoid extra pins.

Idle bus wires are reused as parallel power and shielding paths to cut cross-talk and voltage drops in memory chip interconnects.

Automatic column select timing in a differential memory amplifier cuts control overhead, power use, and read/write timing sensitivity.

Pre-driving the strobe before buffer enablement suppresses reflected-wave distortion and stabilizes multi-phase internal clock generation.

Internal and external CRC comparison speeds memory read and write training while preserving data integrity and controller alignment.

Dual enable signals trigger temperature sensing at setup and during preset operations, keeping internal voltage compensation accurate as conditions change.

A two-stage latch uses one clock phase and a reset-high storage path to cut clock loading, lower power, and speed high-rate operation.

Small-swing signal transfer cuts current and line loading in memory data paths while restoring full-swing output without extra conversion circuits.

Feedback-controlled cross-coupled logic and a tri-state inverter stabilize memory clock buffering at low voltage while reducing timing violations.

By isolating read access to one storage node while using extra write-only connections, this latch circuit reduces soft errors and read data loss.

Divided internal clock phases are sampled at strobe edges and combined to stabilize high-speed phase detection despite signal phase reversals.

Using MTJ-based magnetic logic units, this case shows analog circuits that cut coupling capacitance and 1/f noise while improving switching speed.

A mode-selectable driver and level-shifting receiver let one memory die work across small-swing and full-swing signaling interfaces.

Pushes post-RAM register values and RAM contents backward so retimed logic restores the pre-retiming state on the next clock cycle.

A single resistive switching element adds non-volatile retention to an SRAM cell, enabling fast access with lower power and compact CMOS integration.

Current-driven domain wall motion and MTJ readout enable Boolean logic at lower voltage, cutting transistor heat and power dissipation.

Shared common and individual level shifters generate region-specific assignment signals while reducing semiconductor circuit area.

An MTJ pair, flip-flop, and edge detector preserve sequential logic states through power-down while avoiding false read latching.

A dual-port slave latch lets external data update a flip-flop without slowing the critical timing path, while preserving retention mode storage.

Non-volatile paired memory cells with freeze and test switching cut PLD soft errors and power-on configuration delay.

Variable internal clock delay modulates memory timing to cut EMI from short internal lines while keeping data output synchronized.

A slower-clock pipeline delays memory commands while stored phase information restores timing, cutting flip-flop count, complexity, and power.

Staggered vertical oxide semiconductor transistors share conductors to boost on-state current and integration density while managing device complexity.

A semiconductor device uses a synthesis signal generation circuit to manage bank selection and mode register operations.

A controller configures pass-gates to resolve the read stability versus write speed trade-off in dual-port SRAM circuits.

A memory controller inputs a compensation current to stabilize phase change material resistance in non-volatile storage cells.

Simultaneous memory reads detect unreliable results from low voltage, triggering adjustments that prevent system failures while reducing power consumption.

A memory device measures its own electrical current to dynamically adjust operational performance and restrict write bandwidth.

Segmenting word line signals allows the refresh controller to perform partial updates during idle periods, preventing burst access interruptions.

A non-terminated active DRAM paired with terminated inactive units shapes the memory bus interface to widen the data eye.

Segmenting the memory array into banks with separate source lines reduces switching current requirements while maintaining high integration density.

A data reception chip generates an internal reference voltage using a resistor network to compare incoming signals.

Applying voltage to isolated ferroelectric memory sections discharges capacitors, preventing data corruption from unintended charge storage.

Segmenting write periods with non-coincident pulse peaks reduces peak current requirements while enabling simultaneous multi-cell writing.

A semiconductor structure uses a common bit line to connect storage cells across active pillars.

Replica transistors compensate for parasitic capacitance discharge on deselected columns, preserving voltage difference accuracy across SRAM bit lines.